RC19302A00AGNT#KD0 datasheet(6/62 Pages) RENESAS

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R31DS0210EU0106 Rev.1.06

Page 6

May 11, 2026

RC193xx Datasheet

1.3.2

RC19308 Pin Descriptions

Table 1. RC19308A/A001 Pin Descriptions

Pin Number

Pin Name

Type

Description

ZOUTSEL_tri

I, SE, PD,

Input to select differential output impedance.

0 = 85Ω, 1 = 100Ω, M = 34Ω

Note: This pin is bi-level on the RC19208 clock multiplexer with an internal pull-down,

which results in a default output impedance of 85Ω when left floating.

This pin is tri-level on the RC19308 with both internal pull-up and pull-down resistors.

On the RC19308, this results in a default output impedance of 34Ω when left floating.

This pin must be pulled down or pulled up to select an output impedance of 85Ω or 100Ω,

respectively.

VDDDIG

PWR

Digital power.

PWRGD_PWRDNb

I, SE, PU,

PDT

Input notifies device to sample latched inputs and start up on first high assertion. Low

enters Power Down Mode, subsequent high assertions exit Power Down Mode.

CLKIN0

I, DIF

True clock input.

CLKINb0

I, DIF

Complementary clock input.

VDDIN0

PWR

Power supply for clock input 0.

SADR_tri0

I, SE, PD,

SMBus address bit. This is a tri-level input that works in conjunction with other SADR

pins, if present, to decode SMBus Addresses. See the SMBus Address Selection

(RC19308) table and refer to the tri-level input thresholds in the electrical tables.

CLKIN1

I, DIF

True clock input.

CLKINb1

I, DIF

Complementary clock input.

SDATA

I/O, SE,

OD, PDT Data pin for SMBus interface.

SCLK

I, SE, PDT Clock pin of SMBus interface.

VDDIN1

PWR

Power supply for clock input 1.

VDDCLK_1

PWR

Power supply for clock output bank 1.

CLK7

O, DIF

True clock output.

CLKb7

O, DIF

Complementary clock output.

OEb7

I, SE, PU,

PDT

Active low input for enabling output 7.

0 = Enable output, 1 = Disable output.

CLKSEL_tri

I, SE, PD,

Input to select differential input clock 0 or differential input clock 1. This input has an

internal pull-up and pull-down resistor to bias a floating pin to the mid-point.

0 = CLKIN0 selected for all outputs.

1 = CLKIN1 selected for all outputs.

M = CLKIN0 goes to bank 0 and CLKIN1 goes to bank 1.

OEb6

I, SE, PU,

PDT

Active low input for enabling output 6.

0 = Enable output, 1 = Disable output.

CLK6

O, DIF

True clock output.

CLKb6

O, DIF

Complementary clock output.

VDDCLK_1

PWR

Power supply for clock output bank 1.

CLK5

O, DIF

True clock output.

CLKb5

O, DIF

Complementary clock output.

OEb5

I, SE, PU,

PDT

Active low input for enabling output 5.

0 = Enable output, 1 = Disable output.

OEb4

I, SE, PU,

PDT

Active low input for enabling output 4.

0 = Enable output, 1 = Disable output.

CLK4

O, DIF

True clock output.

CLKb4

O, DIF

Complementary clock output.

VDDCLK_1

PWR

Power supply for clock output bank 1.

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