FN8724 datasheet(17/34 Pages) RENESAS

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ISL98608IIH

FN8724 Rev.2.01

Page 17 of 33

Dec 7, 2021

I2C Digital Interface

The ISL98608IIH uses a standard I2C interface bus for

communication. The two-wire interface links a Master(s) and

uniquely addressable Slave devices. The Master generates clock

signals and is responsible for initiating data transfers. The serial

clock is on the SCL line and the serial data (bidirectional) is on

the SDA line. The ISL98608IIH supports clock rates up to 400kHz

(Fast mode) and is backwards compatible with standard 100kHz

clock rates (Standard mode).

The SDA and SCL lines must be HIGH when the bus is free - not in

use. An external pull-up resistor (typically 2.2kΩ

to 4.7kΩ) or

current source is required for SDA and SCL.

The ISL98608IIH meets standard I2C timing specifications, see

Figure 44 and Table 2, which show the standard timing

definitions and specifications for I2C communication.

START AND STOP CONDITION

All I2C communication begins with a START condition (indicating

the beginning of a transaction) and ends with a STOP condition

(signaling the end of the transaction).

A START condition is signified by a HIGH to LOW transition on the

serial data line (SDA) while the serial clock line (SCL) is HIGH. A

STOP condition is signified by a LOW to HIGH transition on the

SDA line while SCL is HIGH. See timing specifications in Table 2.

The Master always initiates START and STOP conditions. After a

START condition, the bus is considered “busy.” After a STOP

condition, the bus is considered “free.” The ISL98608IIH also

supports repeated STARTs, where the bus will remain busy for

continued transaction(s).

DATA VALIDITY

The data on the SDA line must be stable (clearly defined as HIGH

or LOW) during the HIGH period of the clock signal. The state of

the SDA line can only change when the SCL line is LOW (except to

create a START or STOP condition). See timing specifications in

Table 2.

The voltage levels used to indicate a logical ‘0’ (LOW) and logical

‘1’ (HIGH) are determined by the VIL and VIH thresholds,

respectively, see the “Electrical Specifications” table on page 7.

BYTE FORMAT

Every byte transferred on SDA must be 8 bits in length. After

every byte of data sent by the transmitter there must be an

Acknowledge bit (from the receiver) to signify that the previous

8 bits were transferred successfully. Data is always transferred

on SDA with the Most Significant Bit (MSB) first. See

“Acknowledge (ACK)” on page 18.

FIGURE 44. I2C TIMING DEFINITIONS

tSU:STA

START

tHD:STA

tSU:DAT

tHD:DAT

STOP

START

tBUF

tSU:STO

VIH

VIL

VIH

VIL

SDA

SCL

TABLE 2. I2C TIMING CHARACTERISTICS

PARAMETER

SYMBOL

FAST-MODE

STANDARD-MODE

UNIT

MIN

MAX

MIN

MAX

SCL Clock Frequency

fSCL

400

100

kHz

Set-Up Time for a START Condition

tSU:STA

0.6

4.7

µs

Hold Time for a START Condition

tHD:STA

0.6

4.0

µs

Set-Up Time for a STOP Condition

tSU:STO

0.6

4.0

µs

Bus Free Time between a STOP and START Condition

tBUF

1.3

4.7

µs

Data Set-Up Time

tSU:DAT

100

250

Data Hold Time

tHD:DAT

µs

Rise Time of SDA and SCL (Note 10)tr

20 + 0.1Cb

300

1000

Fall Time of SDA and SCL (Note 10)tf

20 + 0.1Cb

300

Capacitive Load on Each Bus Line (SDA/SCL)

400

NOTE:

10. Cb = Total capacitance of one bus line in pF.

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