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LMKDB1108FS85RKPR Scheda tecnica(PDF) 82 Page - Texas Instruments

Il numero della parte LMKDB1108FS85RKPR
Spiegazioni elettronici  LMKDB11xx PCIe Gen 1 to Gen 7 Ultra Low Jitter LP-HCSL Clock Buffer Family
PDF  133 Pages
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Produttore elettronici  TI2 [Texas Instruments]
Homepage  https://www.ti.com
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LMKDB1108FS85RKPR Scheda tecnica(HTML) 82 Page - Texas Instruments

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Table 9-83. R2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5
RB_OEb_4
R
0h
Status of OEb4
4
RESERVED
R
0h
Reserved
3
RB_OEb_5
R
0h
Status of OEb5
2
RB_OEb_6
R
0h
Status of OEb6
1
RB_OEb_7
R
0h
Status of OEb7
0
RESERVED
R
0h
Reserved
9.4.4 R3 Register (Offset = 3h) [Reset = 00h]
R3 is shown in Table 9-84.
Return to the Summary Table.
Table 9-84. R3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:6
RESERVED
R
0h
Reserved
5
RB_OEb_0
R
0h
Status of OEb0
4:3
RESERVED
R
0h
Reserved
2
RB_OEb_1
R
0h
Status of OEb1
1:0
RESERVED
R
0h
Reserved
9.4.5 R4 Register (Offset = 4h) [Reset = 10h]
R4 is shown in Table 9-85.
Return to the Summary Table.
Table 9-85. R4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:5
RESERVED
R
0h
Reserved
4
AOD_ENABLE
R/W
1h
Enable automatic output disable (AOD) to low/low when LOS event
is detected. Refer to section "Automatic Output Disable" for more
information.
0h = Disabled (DC Coupled)
1h = Enabled (AC Coupled)
3:1
RESERVED
R
0h
Reserved
0
RB_SBI_ENQ
R
0h
Status of SBI_ENQ
9.4.6 R5 Register (Offset = 5h) [Reset = 0Ah]
R5 is shown in Table 9-86.
Return to the Summary Table.
Table 9-86. R5 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
REV_ID
R
0h
Revision ID
3:0
VENDOR_ID
R
Ah
Vendor ID
LMKDB1102, LMKDB1104, LMKDB1104FS, LMKDB1108, LMKDB1108FS
LMKDB1112, LMKDB1120, LMKDB1120FS
SNAS855G – NOVEMBER 2023 – REVISED MAY 2026
www.ti.com
82
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Product Folder Links: LMKDB1102 LMKDB1104 LMKDB1104FS LMKDB1108 LMKDB1108FS LMKDB1112 LMKDB1120 LMKDB1120FS



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