DIO7B104

Version 1.0, Jun 2024

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© 2024 DIOO MICROCIRCUITS CO., LTD.

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10.Function Description

10.1. Architecture

The DIO7B104 architecture (See Figure 6) does not require a direction-control signal to regulate the direction of

data flow from A to B or from B to A. The output drivers of the device maintain high or low, but are designed to be

weak, in a DC state. As a result, when data on the bus flows to the opposite direction, an external driver can

overdrive the output drivers.

The output one-shots on the A or B ports detect rising or falling edges. During a rising edge, the one-shot turns

on the PMOS transistors (T1, T3) for a short duration, which speeds up the low-to-high transition. During a falling

edge, the one-shot turns on the NMOS transistors (T2, T4) for a short duration, which speeds up the high-to-low

transition. 70 Ω at VCCO = 1.2 V to 1.8 V, 50 Ω at VCCO = 1.8 V to 3.3 V, and 40 Ω at VCCO = 3.3 V to 5 V is the

normal output impedance during output transition.

Figure 6. Architecture of DIO7B104 device I/O cell

10.2. Enable and disable

The DIO7B104 device has an OE input that disables the device by setting OE low, which places all I/Os in the

high-impedance (Hi-Z) state. The disable time (tdis) represents the delay between OE going low and the outputs

getting disabled (Hi-Z). The enable time (ten) represents the amount of time that the user must allow a one-shot

circuit to operate after EN is high.