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RA4L1 Scheda tecnica(PDF) 56 Page - Renesas Technology Corp |
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RA4L1 Scheda tecnica(HTML) 56 Page - Renesas Technology Corp |
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56 / 125 page  Table 2.36 SCI timing (1) (2 of 2) Conditions: VCC = AVCC0 = 1.6 to 3.6 V Parameter Symbol Min Max Unit Test conditions SCI Receive data setup time (master) Clock synchronous 1.8 V ≤ VCC ≤ 3.6 V tRXS 40 — ns Figure 2.24 2.4 V ≤ VCC < 2.7 V 50 — 1.8 V ≤ VCC < 2.4 V 70 — 1.6 V ≤ VCC < 1.8 V 110 — Receive data setup time (slave) Clock synchronous 2.4 V ≤ VCC ≤ 3.6 V 10 — ns 1.8 V ≤ VCC ≤ 2.4 V 15 — 1.6 V ≤ VCC < 1.8 V 45 — Receive data hold time (master) Clock synchronous tRXH 5 — ns Receive data hold time (slave) Clock synchronous tRXH 5 — ns tSCKW tSCKr tSCKf tScyc SCKn Note: n = 0, 1, 3 to 5, 9 Figure 2.23 SCK clock input timing tTXD tRXS tRXH TXDn RXDn SCKn Note: n = 0, 1, 3 to 5, 9 Figure 2.24 SCI input/output timing in clock synchronous mode RA4L1 Datasheet 2. Electrical Characteristics R01DS0447EJ0131 Rev.1.31 May 26, 2026 Page 56 of 125 |
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