RZSLASHT2ME datasheet(99/116 Pages) RENESAS

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Table 2.38

Ethernet interface timing (2 of 2)

Parameter

Symbol

Min.

Max.

Unit

Reference

figure

Ethernet

(MII)

ETHn_TXCLK, ETHn_RXCLK cycle

time

100 Mbps

tMIIck

—

Figure 2.84,

Figure 2.85

10 Mbps

400

—

ETHn_TXCLK, ETHn_RXCLK

frequency

100 Mbps

—

25 − 50 ppm

25 + 50 ppm

MHz

10 Mbps

2.5 − 50 ppm

2.5 + 50 ppm

ETHn_TXD0 to ETHn_TXD3, ETHn_TXEN,

ETHn_TXER output delay time

tMIId

ETHn_TXD0 to ETHn_TXD3,

ETHn_TXEN output delay time

(ESC, Automatic TX shift disabled

(ETHn_TXCLK is clamped))

TXSFTn =

00b

tMIIdESC

20.2

25.0

TXSFTn =

01b

30.2

35.0

TXSFTn =

10b

0.2

5.0

TXSFTn = 11b

10.2

15.0

ETHn_RXD0 to ETHn_RXD3, ETHn_RXDV,

ETHn_RXER setup time

tMIIs

—

ETHn_RXD0 to ETHn_RXD3, ETHn_RXDV,

ETHn_RXER hold time

tMIIh

—

Note 1. Measurement condition of tRGMIIr and tRGMIIf is FIGURE 3 in Reduced Gigabit Media Independent Interface (RGMII) 12/10/2000

Version 1.3.

Note 2. Details for each case are as follows:

Case A: ETHn_RXD0, ETHn_RXD1, ETHn_RXER, ETHn_RXDV (CRS_DV) setup time when using ETHn_RXCLK (reference clock

input).

Case B: ETHn_RXD0, ETHn_RXD1, ETHn_RXDV (CRS_DV) setup time when using RMIIn_REFCLK (reference clock output).

Case C: ETHn_RXER setup time when using RMIIn_REFCLK (reference clock output).

Table 2.39

Ethernet interface timing (MAC to MAC connection mode) (1 of 2)

Parameter

Symbol

Min.

Max.

Unit

Reference

figure

Ethernet

(RGMII)

ETH2_TXCLK, ETH2_RXCLK cycle time

tMRGMIIck

7.2

8.8

Figure 2.86

ETH2_TXCLK, ETH2_RXCLK frequency

Typ. 125 MHz

—

125 − 50 ppm

125 + 50 ppm

MHz

ETH2_TXCLK, ETH2_RXCLK duty cycle

—

ETH2_TXCLK, ETH2_TXD0 to ETH2_TXD3,

ETH2_TXEN (TX_CTL), ETH2_RXCLK,

ETH2_RXD0 to ETH2_RXD3, ETH2_RXDV

(RX_CTL) rise/fall time

tMRGMIIr,

tMRGMIIf

—

0.75

ETH2_TXD0 to ETHn_TXD3, ETHn_TXEN

(TX_CTL) output skew

tMRGMIIos

—

0.6

ETH2_TXD0 to ETH2_TXD3, ETH2_TXEN

(TX_CTL) output setup time

tMRGMIIso

1.1

—

ETH2_TXD0 to ETH2_TXD3, ETH2_TXEN

(TX_CTL) output hold time

tMRGMIIho

1.1

—

ETH2_RXD0 to ETH2_RXD3, ETH2_RXDV

(RX_CTL) input setup time

tMRGMIIsi

-0.7

—

ETH2_RXD0 to ETH2_RXD3, ETH2_RXDV

(RX_CTL) input hold time

tMRGMIIhi

2.9

—

RZ/T2ME Datasheet

2. Electrical Characteristics

R01DS0441EJ0110 Rev.1.10

Mar 13, 2026

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