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AS5130

Data Sheet - D e ta i l e d D e s c r i p t i o n

Once the TADC is synchronized with the angle, it sets the LOCK bit in the status register (see Table 9). In worst case,

usually at start-up, the TADC requires a maximum of 127 steps (127 * 1.15µS = 146,05µs) to lock. Once it is locked, it

requires only one cycle (1.15µs) to track the moving magnet.

The AS5130 can operate in locked mode at rotational speeds up to 30,000 rpm.

In Low Power Mode, the position of the TADC is frozen. It will continue from the frozen position once it is powered up

again. If the magnet has moved during the power down phase, several cycles will be required before the TADC is

locked again. The tracking time to lock in with the new magnet angle can be roughly calculated as:

(EQ 3)

Where:

OldPos = Angle position when one of the reduced power modes is activated [º]

NewPos = Angle position after resuming from reduced power mode [º]

Propagation Delay

The Propagation delay is the time required from reading the magnetic field by the Hall sensors to calculating the angle

and making it available on the serial or PWM interface. While the propagation delay is usually negligible on low

speeds, it is an important parameter at high speeds. The longer the propagation delay, the larger becomes the angle

error for a rotating magnet as the magnet is moving while the angle is calculated. The position error increases linearly

with speed. The main factors that contribute to the propagation delay are discussed in detail further in this document.

Sampling Rate

For high speed applications, fast ADC’s are essential. The ADC sampling rate directly influences the propagation

delay. The fast tracking ADC used in the AS5130 with a tracking rate of only 1.15µs (typ) is a perfect fit for both high

speed and high performance.

Chip Internal Lowpass Filtering

A commonplace practice for systems using analog-to-digital converters is to filter the input signal by an anti-aliasing

filter. The filter characteristic must be chosen carefully to balance propagation delay and noise. The lowpass filter in the

AS5130 has a cutoff frequency of typ. 23.8kHz and the overall propagation delay in the analog signal path is typ.

15.6µs.

Digital Readout Rate

Aside from the chip-internal propagation delay, the time required to read and process the angle data must also be

considered. Due to its nature, a PWM signal is not very usable at high speeds, as you get only one reading per PWM

period. Increasing the PWM frequency may improve the situation but causes problems for the receiving controller to

resolve the PWM steps. The frequency on the AS5130 PWM output is typ. 1.95kHz with a resolution of 2µs/step. A

more suitable approach for high speed absolute angle measurement is using the serial interface. With a clock rate of

up to 6MHz, a complete set of data (21bits) can be read in >3.5µs.

Total Propagation Delay of the AS5130

The total propagation delay of the AS5130 is the delay in the analog signal path and the tracking rate of the ADC:

15.6µs + 1.15µs = 16.75µs

(EQ 4)

If only the SIN-/COS-outputs are used, the propagation delay is the analog signal path delay only (typ. 15.6µs).

Position Error Over Speed:

The angle error over speed caused by the propagation delay is calculated as:

(EQ 5)