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Programmable Gain

Power Down

ADS5517

SLWS203 – DECEMBER 2007

ADS5517 has programmable gain from 0 dB to 6 dB in steps of 1 dB. The corresponding full-scale input range

varies from 2 VPP down to 1 VPP, with 0 dB being the default gain. At high IF, this is especially useful as the

SFDR improvement is significant with marginal degradation in SNR.

The gain can be programmed using the serial interface (bits D3-D0 in register 0x68).

ADS5517 has three power-down modes – global STANDBY, output buffer disabled, and input clock stopped.

Global STANDBY

This mode can be initiated by controlling SDATA (pin 28) or by setting the register bit <STBY> (Table 10)

through the serial interface. In this mode, the A/D converter, reference block and the output buffers are powered

down and the total power dissipation reduces to about 100 mW. The output buffers are in high impedance state.

The wake-up time from the global power down to data becoming valid normal mode is maximum 100

µs.

Output Buffer Disable

The output buffers can be disabled using OE pin 7 in both the LVDS and CMOS modes, reducing the total power

by about 100 mW. With the buffers disabled, the outputs are in high impedance state. The wake-up time from

this mode to data becoming valid in normal mode is maximum 1

µs in LVDS mode and 50 ns in CMOS mode.

Input Clock Stop

The converter enters this mode when the input clock frequency falls below 1 MSPS. The power dissipation is

about 100 mW and the wake-up time from this mode to data becoming valid in normal mode is maximum 100

µs.

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