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ADS5517 Scheda tecnica(PDF) 24 Page - Texas Instruments

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Il numero della parte ADS5517
Spiegazioni elettronici  11-BIT, 200 MSPS ADC
PDF  54 Pages
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
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ADS5517 Scheda tecnica(HTML) 24 Page - Texas Instruments

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PIN CONFIGURATION (CMOS MODE)
DRGND
DRVDD
OVR
UNUSED
CLKOUT
DFS
OE
AVDD
AGND
CLKP
CLKM
AGND
1
2
3
4
5
6
7
8
9
10
11
12
DRGND
DRVDD
NC
NC
NC
NC
RESET
SCLK
SDATA
SEN
AVDD
AGND
36
35
34
33
32
31
30
29
28
27
26
25
ThermalPad
ADS5517
SLWS203 – DECEMBER 2007
RGZ PACKAGE
(TOP VIEW)
Figure 8. CMOS Mode Pinout
PIN ASSIGNMENTS – CMOS Mode
PIN
PIN
NUMBER
PIN NAME
DESCRIPTION
TYPE
NUMBER
OF PINS
8, 18, 20,
AVDD
Analog power supply
I
6
22, 24, 26
9, 12, 14, 17,
AGND
Analog ground
I
6
19, 25
CLKP, CLKM
Differential clock input
I
10, 11
2
INP, INM
Differential analog input
I
15, 16
2
Internal reference mode – Common-mode voltage output.
VCM
External reference mode – Reference input. The voltage forced on this pin sets the
I/O
13
1
internal references.
IREF
Current-set resistor, 56.2-k
Ω resistor to ground.
I
21
1
Serial interface RESET input.
When using the serial interface mode, the user MUST initialize internal registers
through hardware RESET by applying a high-going pulse on this pin, or by using
the software reset option. See the SERIAL INTERFACE section.
RESET
I
30
1
In parallel interface mode, the user has to tie RESET pin permanently HIGH.
(SDATA and SEN are used as parallel pin controls in this mode).
The pin has an internal 100-k
Ω pull-down resistor.
This pin functions as serial interface clock input when RESET is low.
It functions as LOW SPEED control pin when RESET is tied high. Tie SCLK to
SCLK
I
29
1
LOW for Fs > 50 MSPS and SCLK to HIGH for Fs
≤ 50 MSPS. See Table 3.
The pin has an internal 100-k
Ω pull-down resistor.
24
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Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS5517



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