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ADS5517

SLWS203 – DECEMBER 2007

Table 10. Serial Register B

A7 – A0 (hex)

<DF>

<STBY>

DATA

ENABLE LOW

GLOBAL

FORMAT

SAMPLING

POWER

2's COMP or

FREQUENCY

DOWN

STRAIGHT

OPERATION

BINARY

<DF> Output data format

2's complement

Straight binary

<LOW SPEED> Low sampling frequency operation

Default SPEED mode for 50 < Fs

≤ 200 MSPS

Low SPEED mode 1

≤ Fs ≤ 50 MSPS

<STBY> Global power down

Normal operation

Global power down (includes ADC, internal references and output buffers)

Table 11. Serial Register C

A7 – A0 (hex)

<TEST PATTERNS> — ALL 0S, ALL 1s,

TOGGLE, RAMP, CUSTOM PATTERN

D7 — D5

<TEST PATTERN> Outputs selected test pattern on data lines

000

Normal operation

001

All 0s

010

All 1s

011

Toggle pattern – alternate 1s and 0s on each data output and across

data outputs

100

Ramp pattern – Output data ramps from 0x0000 to 0x3FFF by one

code every clock cycle

101

Custom pattern – Outputs the custom pattern in CUSTOM PATTERN

registers A and B

111

Unused

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