ADMV4530 datasheet(9/64 Pages) AD

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Data Sheet

ADMV4530

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. C | 9 of 64

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 12, 40

VCC_DRV, VCC_AMP, VCC2_DRV

Supply Voltages for the RF Output Driver, 4.0 V. Place a 1 µF decoupling capacitor close to each pin.

2, 3, 14

No Connection.

VCTR_RF

RF Gain Control, 0 V to 1.8 V. Apply voltage to VCTR_RF after all other supply pins have been powered. If that is not

possible, then be sure to install approximately 1 kΩ in series with VCTR_RF.

5, 6, 8, 9

QN, QP, IP, IN

Differential Quadrature Baseband Inputs. These 100 Ω differential impedance inputs can be common-mode dc biased

from 0 V to 2.5 V.

7, 16

VCC_IF, VCC2_IF

Supply Voltages for the IF and Baseband Inputs, 3.3 V. Place a 1 µF decoupling capacitor close to each pin.

EXT_CAP_N (VCTR_IF)

IF Gain Control Capacitor Negative Terminal. To adjust the IF gain manually, this pin must be driven externally when

the AGC functionality is disabled, 0 V to 3.3 V. Note that VCTR_IF is the voltage applied to the EXT_CAP_x pins.

Apply voltage to EXT_CAP_N after all other supply pins have been powered. If that is not possible, then be sure to

install approximately 1 kΩ in series with EXT_CAP_N.

EXT_CAP_P

IF Gain Control Capacitor Positive Terminal. Note that VCTR_IF is the voltage applied to the EXT_CAP_x pins.

VCC_VVA

Supply Voltage for the Variable Gain Amplifier, 1.8 V. Place a 1 µF decoupling capacitor close to this pin.

VCC_MIXER

Supply Voltage for the Mixer, 3.3 V. Place a 1 µF decoupling capacitor close to this pin.

VCC_DOUBLER

Supply Voltage for the Internal 2× Multiplier, 3.3 V. Place a 1 µF decoupling capacitor close to this pin.

IF Input. This pin has a 50 Ω input impedance.

RBIAS

Resistor Band Gap Reference Bias. Place a precision 680 Ω resistor to ground at this pin.

VTUNE

VCO Tune Port, 0.5 V to 2.8 V. This pin is driven by the output of the loop filter.

VCC_BG

Supply Voltage for the Internal Band Gap, 3.3 V. Place a 1 µF decoupling capacitor close to this pin.

VG_VCO

VCO Gate Decoupling. Place a 10 µF decoupling capacitor at this pin.

VCC_VCO

Supply Voltage for the VCO, 3.3 V. Place a 1 µF decoupling capacitor close to this pin.

VCC_DIV

Supply Voltage for Fractional-N PLL, 3.3 V. Place a 1 µF decoupling capacitor close to this pin.

Power-Down, 3.3 V Logic. Active high.

CPOUT

Charge Pump Output. Connect this pin to VTUNE (Pin 20) through the loop filter.

SPI Chip Select. 3.3 V logic. Active low.

SDI

SPI Data Input. 3.3 V logic.

SCLK

SPI Clock. 3.3 V logic.

SDO

SPI Data Output. 3.3 V logic.

CREG

External Capacitor for the Low Dropout (LDO) Regulator Output. Place a 0.1 µF decoupling capacitor close to this pin.

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