V58C265404S datasheet(6/44 Pages) MOSEL

6 / 44 page

V58C265404S Rev. 1.4 January 2000

MOSEL VITELIC

V58C265404S

Mode Register Set (MRS)

The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs

CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to

make DDR SDRAM useful for a variety of different applications. The default value of the mode register is not

defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation.

The mode register is written by asserting low on CS, RAS, CAS, WE and BA0 (The DDR SDRAM should be

in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins

A0 ~ A11 in the same cycle as CS, RAS, CAS, WE and BA0 low is written in the mode register. Two clock

cycles are required to meet tMRD spec. The mode register contents can be changed using the same com-

mand and clock cycle requirements during operation as long as all banks are in the idle state. The mode reg-

ister is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode

uses A3, CAS latency (read latency from column address) uses A4 ~ A6. A7 is a Mosel Vitelic specific test

mode during production test. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer

to the table for specific codes for various burst length, addressing modes and CAS latencies.

MRS can be issued only at all banks precharge state.

Minimum tRP is required to issue MRS command.

Address Bus

CAS Latency

Latency

Reserve

2.5

Reserve

Burst Length

Latency

Sequential

Interleave

Reserve

mode

Normal

Test

Burst Type

Sequential

Interleave

* RFU(Reserved for future use)

should stay "0" during MRS

cycle.

DLL Reset

Yes

Mode Register Set

RFU : Must be set "0"

Extended Mode Register

Mode Register

DLL

I/O

DLL Enable

Enable

Disable

I/O Strength

Full

Half

BA0

An ~ A0

(Existing)MRS Cycle

Extended Funtions(EMRS)

Command

CK, CK

tCK

tMRD

Precharge

All Banks

Mode

tRP*2

Any

Command

BA1

BA 0

A11

A10

CAS Latency

Burst Length

RFU

DLL

MRS

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