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V58C265404S Scheda tecnica(PDF) 7 Page - Mosel Vitelic, Corp |
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V58C265404S Scheda tecnica(HTML) 7 Page - Mosel Vitelic, Corp |
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7 / 44 page ![]() 7 V58C265404S Rev. 1.4 January 2000 MOSEL VITELIC V58C265404S Mode Register Set Timing Burst Mode Operation Burst Mode Operation is used to provide a constant flow of data to memory locations (Write cycle), or from memory locations (Read cycle). Two parameters define how the burst mode will operate: burst sequence and burst length. These parameters are programmable and are determined by address bits A0—A3 during the Mode Register Set command. Burst type defines the sequence in which the burst data will be delivered or stored to the SDRAM. Two types of burst sequence are supported: sequential and interleave. The burst length controls the number of bits that will be output after a Read command, or the number of bits to be input after a Write command. The burst length can be programmed to values of 2, 4, or 8. See the Burst Length and Sequence table below for programming information. Burst Length and Sequence Burst Length Starting Length (A2, A1, A0) Sequential Mode Interleave Mode 2 xx0 0, 1 0, 1 xx1 1, 0 1, 0 4 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 8 000 0,1, 2, 3, 4, 5, 6, 7 0,1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5, 6 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 T5 T0 T1 T2 T3 T4 T6 T7 T8 tRP tMRD tCK Pre- All MRS/EMRS ANY Mode Register set (MRS) or Extended Mode Register Set (EMRS) can be issued only when all banks are in the idle state. CK, CK Command If a MRS command is issued to reset the DLL, then an additional 200 clocks must occur prior to issuing any new command T9 to allow time for the DLL to lock onto the clock. |
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