MSC8113 datasheet(39/44 Pages) FREESCALE

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Hardware Design Considerations

MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semiconductor

Each VCC and VDD pin on the MSC8113 device should have a low-impedance path to the board power supply. Similarly, each

GND

pin should have a low-impedance path to the ground plane. The power supply pins drive distinct groups of logic on the

chip. The VCC power supply should have at least four 0.1 µF by-pass capacitors to ground located as closely as possible to the

four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip VCC, VDD, and GND should

be kept to less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and

GND

planes.

All output pins on the MSC8113 have fast rise and fall times. PCB trace interconnection length should be minimized to

minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to

the address and data buses. Maximum PCB trace lengths of six inches are recommended. For the DSI control signals in

synchronous mode, ensure that the layout supports the DSI AC timing requirements and minimizes any signal crosstalk.

Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PCB traces. Attention to

proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create

higher transient currents in the VCC, VDD, and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.

Special care should be taken to minimize the noise levels on the PLL supply pins. There is one pair of PLL supply pins:

VCCSYN-GNDSYN. To ensure internal clock stability, filter the power to the VCCSYN input with a circuit similar to the one in

Figure 33. For optimal noise filtering, place the circuit as close as possible to VCCSYN. The 0.01-µF capacitor should be closest

to VCCSYN, followed by the 10-µF capacitor, the 10-nH inductor, and finally the 10-Ω resistor to VDD. These traces should be

kept short and direct. Provide an extremely low impedance path to the ground plane for GNDSYN. Bypass GNDSYN to VCCSYN

by a 0.01-µF capacitor located as close as possible to the chip package. For best results, place this capacitor on the backside of

the PCB aligned with the depopulated void on the MSC8113 located in the square defined by positions, L11, L12, L13, M11,

M12, M13, N11, N12, and N13.

3.3

Connectivity Guidelines

Unused output pins can be disconnected, and unused input pins should be connected to the non-active value, via resistors to

VDDH or GND, except for the following:

•

If the DSI is unused (DDR[DSIDIS] is set), HCS and HBCS must pulled up and all the rest of the DSI signals can be

disconnected.

•

When the DSI uses synchronous mode, HTA must be pulled up. In asynchronous mode, HTA should be pulled either

up or down, depending on design requirements.

•

HDST

can be disconnected if the DSI is in big-endian mode, or if the DSI is in little-endian mode and the

DCR[DSRFA] bit is set.

•

When the DSI is in 64-bit data bus mode and DCR[BEM] is cleared, pull up HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/

HDBE[1–3]

and HWBS[4–7]/HDBS[4–7]/HWBE[4–7]/HDBE[4–7]/PWE[4–7]/PSDDQM[4–7]/PBS[4–7].

•

When the DSI is in 32-bit data bus mode and DCR[BEM] is cleared, HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/HDBE[1–3]

must be pulled up.

•

When the DSI is in asynchronous mode, HBRST and HCLKIN should either be disconnected or pulled up.

•

The following signals must be pulled up: HRESET, SRESET, ARTRY, TA, TEA, PSDVAL, and AACK.

•

In single-master mode (BCR[EBM] = 0) with internal arbitration (PPC_ACR[EARB] = 0):

— BG, DBG, and TS can be left unconnected.

— EXT_BG[2–3], EXT_DBG[2–3], and GBL can be left unconnected if they are multiplexed to the system bus

functionality. For any other functionality, connect the signal lines based on the multiplexed functionality.

— BR must be pulled up.

— EXT_BR[2–3] must be pulled up if multiplexed to the system bus functionality.

Figure 33. VCCSYN Bypass

VDD

0.01 µF

10 µF

VCCSYN

10nH

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