MSC8113 datasheet(19/44 Pages) FREESCALE

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Electrical Characteristics

MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semiconductor

2.5.4.1

Power-On Reset (PORESET) Pin

Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 16 CLKIN cycles after

VDD and VDDH are both at their nominal levels.

2.5.4.2

Reset Configuration

The MSC8113 has two mechanisms for writing the reset configuration:

•

Through the direct slave interface (DSI)

•

Through the system bus. When the reset configuration is written through the system bus, the MSC8113 acts as a

configuration master or a configuration slave. If configuration slave is selected, but no special configuration word is

written, a default configuration word is applied.

Fourteen signal levels (see Chapter 1 for signal description details) are sampled on PORESET deassertion to define the Reset

Configuration Mode and boot and operating conditions:

•

RSTCONF

•

CNFGS

•

DSISYNC

•

DSI64

•

CHIP_ID[0–3]

•

BM[0–2]

•

SWTE

•

MODCK[1–2]

Table 11. Reset Actions for Each Reset Source

Reset Action/Reset Source

Power-On

Reset

(PORESET)

Hard Reset (HRESET)

Soft Reset (SRESET)

External only

External or Internal

(Software Watchdog or

Bus Monitor)

External

JTAG Command:

EXTEST, CLAMP, or

HIGHZ

Configuration pins sampled (Refer to

Section 2.5.4.1 for details).

Yes

NoNoNo

SPLL state reset

Yes

System reset configuration write through

the DSI

Yes

NoNoNo

System reset configuration write though

the system bus

Yes

HRESET driven

Yes

SIU registers reset

Yes

IPBus modules reset (TDM, UART,

Timers, DSI, IPBus master, GIC, HS, and

GPIO)

Yes

SRESET driven

Yes

Depends on command

SC140 extended cores reset

Yes

MQBS reset

Yes

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