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R5F64110DFB Scheda tecnica(PDF) 58 Page - Renesas Technology Corp |
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R5F64110DFB Scheda tecnica(HTML) 58 Page - Renesas Technology Corp |
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58 / 84 page ![]() R01DS0062EJ0130 Rev.1.30 Page 58 of 93 Mar 3, 2014 R32C/111 Group 5. Electrical Characteristics Note: 1. The device is operationally guaranteed under these operating conditions. Figure 5.1 Clock Cycle Time Table 5.5 Operating Conditions (4/5) (VCC1 =VCC2 = 3.0 to 5.5 V, VSS =0 V, and Ta =Topr, unless otherwise noted) (1) Symbol Characteristic Value Unit Min. Typ. Max. f(XIN) Main clock oscillator frequency 416 MHz f(XRef) Reference clock frequency 24 MHz f(PLL) PLL clock oscillator frequency 96 128 MHz f(Base) Base clock frequency 50 MHz tc(Base) Base clock cycle time 20 ns f(CPU) CPU operating frequency 50 MHz tc(CPU) CPU clock cycle time 20 ns f(BCLK) Peripheral bus clock operating frequency 25 MHz tc(BCLK) Peripheral bus clock cycle time 40 ns f(PER) Peripheral clock source frequency 32 MHz f(XCIN) Sub clock oscillator frequency 32.768 62.5 kHz Base clock (internal signal) t c(Base) Peripheral bus clock (internal signal) t c(BCLK) CPU clock (internal signal) t c(CPU) |
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