R5F64110DFB datasheet(63/84 Pages) RENESAS

63 / 84 page

R01DS0062EJ0130 Rev.1.30

Page 63 of 93

Mar 3, 2014

R32C/111 Group

5. Electrical Characteristics

Timing Requirements (VCC1 = VCC2 = 3.0 to 5.5 V, VSS =0 V, and Ta = Topr, unless otherwise noted)

Figure 5.5

Flash Memory CPU Rewrite Mode Timing

Table 5.14

Flash Memory CPU Rewrite Mode Timing

Symbol

Characteristics

Value

Unit

Min.

Max.

tcR

Read cycle time

200

tsu(S-R)

Chip-select setup time before read

200

th(R-S)

Chip-select hold time after read

0ns

tsu(A-R)

Address setup time before read

200

th(R-A)

Address hold time after read

0ns

tw(R)

Read pulse width

100

tcW

Write cycle time

200

tsu(S-W)

Chip-select setup time before write

0ns

th(W-S)

Chip-select hold time after write

tsu(A-W)

Address setup time before write

0ns

th(W-A)

Address hold time after write

tw(W)

Write pulse width

Chip select

Address

t h(R-S)

Read cycle

t w(R)

t su(S-R)

t h(R-A)

t su(A-R)

Write cycle

Chip select

Address

t h(W-S)

t w(W)

t su(S-W)

t h(W-A)

t su(A-W)

t cW

t cR

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