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HS4318ESS01H Scheda tecnica(PDF) 41 Page - Renesas Technology Corp |
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HS4318ESS01H Scheda tecnica(HTML) 41 Page - Renesas Technology Corp |
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41 / 68 page ![]() HD404318 Series 39 Bit Initial value Read/Write Bit name 3 0 W TMC3 2 0 W TMC2 0 0 W TMC0 1 0 W TMC1 Timer mode register C (TMC: $00D) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2048tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc TMC2 TMC0 TMC1 Input Clock Period TMC3 0 1 Free-Running/Reload Timer Selection Free-running timer Reload timer 1024tcyc Figure 29 Timer Mode Register C (TMC) T (N + 1) T 256 T T (256 – N) × × × TMC3 = 0 (Free-running timer) TMC3 = 1 (Reload timer) Notes: T: Input clock period supplied to counter. (The clock source and system clock division ratio are determined by timer mode register C.) N: Value of timer write register C. (When N = 255 ($FF), PWM output is fixed low.) Figure 30 PWM Output Waveform |
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