7641 datasheet(36/138 Pages) RENESAS

36 / 138 page

7641 Group

Rev.4.00

Aug 28, 2006

page 36 of 135

REJ03B0191-0400

qReceive Errors

If there is an error, it is detected at the same time that data is

transferred from the receive shift register to the receive buffer reg-

ister, and the Receive Buffer Full Flag is set to “1”. The all error

flags PER, FER, OER and SER are cleared to “0” when the

UARTx status register is read, at the hardware reset or initializa-

tion by setting the Transmit Initialization Bit.

The Summing Error Flag (SER) is set to “1” when any one of the

PER, FER and OER is set to “1”.

The Parity Error Flag (PER) is set to “1” when the sum total of 1s

of received data and the parity does not correspond with the se-

lection with the Parity Select Bit (PMD). It is enabled only if the

Parity Enable Bit (bit 5 of UxMOD) is set to “1”.

The Framing Error Flag (FER) is set to “1” when the number of

stop bit of the received data does not correspond with the selec-

tion with the Stop Bit Length Select Bit (STB).

The Overrun Flag Flag (OER) is set to “1” if the previous data in

the low-order byte of the receive buffer register 1 (addresses

003416, 003C16) is not read before the current receive operation is

completed. It is also set “1” if any one of error flags is “1” for the

previous data and the current receive operation is completed. Be

sure to read UARTx status register to clear the error flags before

the next reception has been completed.

[UARTx (x = 1, 2) Control Register (UxCON)] 003316, 003B16

The UARTx control register consists of eight control bits for the

UARTx function. This register can enable the CTS, RTS and

UART address mode.

If the Transmit Enable Bit (TEN) is set to “0” (disabled) while a

data is being transmitted, the transmitting operation will stop after

the data has been transmitted. If the Receive Enable Bit (REN) is

set to “0” (diabled) while a data is being received, the receiving

operation will stop after the data has been received.

When setting the Transmit Initialization Bit (TIN) to “1”, the TEN bit

is set to “0” and the UARTx status register will be set to “0316” af-

ter the data has been transmitted. To retransmit, set the TEN to “1”

and set a data to the transmit buffer register again. The TIN bit will

be cleared to “0” one cycle later after the TIN bit has been set to

“1”.

Setting the Receive Initialization Bit (RIN) to “1” sets all of the

REN, RBF and the receive error flags (PER, FER, OER, SER) to

“0”. The RIN bit will be cleared to “0” one cycle later after the RIN

bit has been set to “1”.

When CTS or RTS function is disabled, pins CTS1 and CTS2 or

RTS1 and RTS2 can be used as ordinary I/O ports, correspond-

ingly.

[UARTx Transmit/Receive Buffer Registers 1, 2 (UxTRB1/

UxTRB2)] 003416, 003516, 003C16, 003D16

The transmit buffer register and the receive buffer register are lo-

cated at the same address. The transmit buffer register is

write-only and the receive buffer register is read-only. If a charac-

ter bit length is 7 bits, the MSB of received data is invalid. If a

character bit length is 7 or 8 bits, the received contents of UxTRB2

are also invalid. If a character bit length is 9 bits, the received

high-order 7 bits of UxTRB2 are “0”.

[UARTx (x = 1, 2) RTS Control Register (UxRTS)] 003616,

003E16

The delay time from the reception of the last stop bit to the asser-

tion of RTSx is selectable using the RTS Assertion Delay Count

Select Bits. If the stop bit is detected before RTS assertion delay

time has expired, the RTSx pin is kept “H”. The RTS assertion de-

lay count starts after the last data reception is completed.

Setting the RIN bit to “1” resets the UxRTS. After setting the RIN

bit to “1”, set this UxRTS.

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