M38063M2AFP datasheet(41/58 Pages) RENESAS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

_____

Before

φ ONW input set up time

_____

After

φ ONW input hold time

Before

φ data bus set up time

After

φ data bus hold time

___ _____

Before RD ONW input set up time

___ _____

Before WR ONW input set up time

___ _____

After RD ONW input hold time

___ _____

After WR ONW input hold time

___

Before RD data bus set up time

___

After RD data bus hold time

____

tsu(ONW–

φ)

____

th(

φ–ONW)

tsu(DB–

φ)

th(

φ–DB)

____ __

tsu(ONW–RD)

____ ___

tsu(ONW–WR)

____

th(RD–ONW)

___ ____

th(WR–ONW)

tsu(DB–RD)

th(RD–DB)

Symbol

Parameter

Limits

Min.

Unit

–20

180

–20

185

Typ.

Max.

φ clock cycle time

φ clock “H” pulse width

φ clock “L” pulse width

After

φ AD15–AD8 delay time

After

φ AD15–AD8 valid time

After

φ AD7–AD0 delay time

After

φ AD7–AD0 valid time

SYNC delay time

SYNC valid time

___

RD and WR delay time

___

RD and WR valid time

After

φ data bus delay time

After

φ data bus valid time

___

RD pulse width, WR pulse width

___

RD pulse width, WR pulse width

(when one-wait is valid)

___

After AD15–AD8 RD delay time

___

After AD15–AD8 WR delay time

___

After AD7–AD0 RD delay time

___

After AD7–AD0 WR delay time

___

After RD AD15–AD8 valid time

___

After WR AD15–AD8 valid time

___

After RD AD7–AD0 valid time

___

After WR AD7–AD0 valid time

___

After WR data bus delay time

___

After WR data bus valid time

_________

RESETOUT output delay time (Note 1)

_________

RESETOUT output valid time (Note 1)

Symbol

Parameter

Limits

Min.

Unit

tc(XIN)–20

3tc(XIN)–20

tc(XIN)–145

2tc(XIN)

150

200

195

300

Typ.

Max.

tc(

φ)

twH(

φ)

twL(

φ)

td(

φ–AH)

tv(

φ–AH)

td(

φ–AL)

tv(

φ–AL)

td(

φ–SYNC)

tv(

φ–SYNC)

___

td(

φ–WR)

___

tv(

φ–WR)

td(

φ–DB)

tv(

φ–DB)

twL(RD)

___

twL(WR)

td(AH–RD)

___

td(AH–WR)

td(AL–RD)

___

td(AL–WR)

tv(RD–AH)

___

tv(WR–AH)

tv(RD–AL)

___

tv(WR–AL)

___

td(WR–DB)

___

tv(WR–DB)

___ _____

td(RESET–RESETOUT)

_____

tv(

φ–RESET)

Test conditions

Fig. 32

Note1:

__________

The RESETOUT output goes “H” in sync with the fall of the

φ clock that is anywhere between about 8 cycle and 13 cycles after

______

the RESET input goes “H”.

TIMING REQUIREMENTS 2 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE

(VCC = 3.0 V, VSS = 0 V, Ta = –20 to 85

°C, unless otherwise noted)

SWITCHING CHARACTERISTICS 2 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE

(VCC = 3.0 V, VSS = 0 V, Ta = –20 to 85

°C, unless otherwise noted)

MITSUBISHI MICROCOMPUTERS

3806 Group

M38063M2AFP Scheda tecnica(PDF) 41 Page - Renesas Technology Corp

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