M38063M2AFP datasheet(45/58 Pages) RENESAS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

TIMING REQUIREMENTS (Extended operating temperature version)

Note: When bit 6 of address 001A16 is “1”. Divide this value by four when bit 6 of address 001A16 is “0”.

Reset input “L” pulse width

External clock input cycle time

External clock input “H” pulse width

External clock input “L” pulse width

CNTR0, CNTR1 input cycle time

CNTR0, CNTR1 input “H” pulse width

INT0 to INT4 input “H” pulse width

CNTR0, CNTR1 input “L” pulse width

INT0 to INT4 input “L” pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O2 clock input cycle time

Serial I/O1 clock input “H” pulse width (Note)

Serial I/O2 clock input “H” pulse width

Serial I/O1 clock input “L” pulse width (Note)

Serial I/O2 clock input “L” pulse width

Serial I/O1 input set up time

Serial I/O2 input set up time

Serial I/O1 input hold time

Serial I/O2 input hold time

_____

tw(RESET)

tc(XIN)

twH(XIN)

twL(XIN)

tc(CNTR)

twH(CNTR)

twH(INT)

twL(CNTR)

twL(INT)

tc(SCLK1)

tc(SCLK2)

twH(SCLK1)

twH(SCLK2)

twL(SCLK1)

twL(SCLK2)

tsu(RXD–SCLK1)

tsu(SIN2–SCLK2)

th(SCLK1–RXD)

th(SCLK2–SIN2)

Symbol

Parameter

Limits

Min.

µs

Unit

125

200

800

1000

370

400

370

400

220

200

100

200

Typ.

Max.

Serial I/O1 clock output “H” pulse width

Serial I/O1 clock output “L” pulse width

Serial I/O1 output delay time (Note 1)

Serial I/O1 output valid time (Note 1)

Serial I/O1 clock output rise time

Serial I/O1 clock output fall time

Serial I/O2 clock output “H” pulse width

Serial I/O2 clock output “L” pulse width

Serial I/O2 output delay time

Serial I/O2 output valid time

Serial I/O2 clock output fall time

CMOS output rise time (Note 2)

CMOS output fall time (Note 2)

140

200

Symbol

Parameter

Limits

Min.

Unit

tc(SCLK1)/2–30

–30

tc(SCLK2)/2–160

Typ.

Max.

twH(SCLK1)

twL(SCLK1)

td(SCLK1–TXD)

tv(SCLK1–TXD)

tr(SCLK1)

tf(SCLK1)

twH(SCLK2)

twL(SCLK2)

td(SCLK2–SOUT2)

tv(SCLK2–SOUT2)

tf(SCLK2)

tr(CMOS)

tf(CMOS)

Test conditions

Fig. 32

Fig. 33

Fig. 32

Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2: Pins XOUT pin and P70–P77 are excluded.

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85

°C, unless otherwise noted)

SWITCHING CHARACTERISTICS (Extended operating temperature version)

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85

°C, unless otherwise noted)

MITSUBISHI MICROCOMPUTERS

3806 Group

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