M32CSLASH8A datasheet(80/372 Pages) RENESAS

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M32C/8A Group

8. Bus

Rev.1.00

Jul 15, 2007

Page 63 of 352

REJ09B0385-0100

8.2.5

ALE Output

The ALE output signal is provided for the external devices to latch the address when using the multiplexed bus.

Latch the address at the falling edge of the ALE output. Bits PM15 and PM14 in the PM1 register determine to

what pin the ALE output is assigned.

The ALE signal is output even when accessing the internal space.

Figure 8.10

ALE Output and Address/Data Bus

8.2.6

RDY Input

The RDY signal facilitates access to external devices requiring longer access time. When RDY input is “L” at

the falling edge of the last BCLK cycle, wait states are inserted into the bus cycle. Then, when an “H” signal is

input to the RDY pin at the falling edge of BCLK, the MCU resumes executing the remaining bus clock.

Table 8.7 lists MCU states when placed in wait state by RDY input. Figure 8.11 shows an example of the RD

signal that is extended by the RDY signal.

Table 8.7

MCU States while “L” is Input to the RDY Pin

Item

State

Clock generation circuits

Operating (oscillating)

RD, WR, A0 to A22, A23, D0 to D15, CS0 to CS3, ALE,

HLDA, programmable I/O ports

Maintains the same state as when “L” is input to RDY pin.

Internal peripheral circuits

Operating

(1) 8-bit data bus

ALE

D0/A0 to D7/A7

NOTE:

1. D0/A0 to D15/A15 are placed in high-impedance states when read.

Address

Data(1)

Address

Address or CS

A8 to A15

A16 to A19

A20/CS3

A21/CS2

A22/CS1

A23/CS0

ALE

D0/A0 to D15/A15

Address

Data(1)

Address

Address or CS

A16 to A19

(2) 16-bit data bus

A20/CS3

A21/CS2

A22/CS1

A23/CS0

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