M32CSLASH8A datasheet(91/372 Pages) RENESAS

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M32C/8A Group

9. Clock Generation Circuits

Rev.1.00

Jul 15, 2007

Page 74 of 352

REJ09B0385-0100

Figure 9.5

CM2 Register

b6 b5 b4

Oscillation Stop Detection Register(1)

Symbol

CM2

Address

000Dh

Bit Symbol

Bit Name

CM20

After Reset

00h

NOTES:

1. Set the CM2 register after the PRC0 bit in the PRCR register is set to 1 (write enable).

2. If the PM21 bit in the PM2 register is set to 1 (disables a clock change), a write to the CM20 bit has no effect.

3. When a loss of the main clock is detected while the CM20 bit is set to 1, the CM21 bit becomes 1.

Although the main clock restarts oscillating, the CM21 bit does not become 0. To use the main clock as the CPU clock source

after the main clock restarts oscillating, set the CM21 bit to 0 by program.

4. When both the CM20 and CM22 bits are set to 1, do not set the CM21 bit to 0.

5. When a loss of the main clock is detected, the CM22 bit becomes 1. The CM22 bit can only be set to 0, not 1, by program.

If the CM22 bit is set to 0 by program while the main clock is stopped, the CM22 bit does not become 1 until another loss of the

main clock is detected after the main clock restarts oscillating.

6. Determine the main clock state by reading the CM23 bit several times after the oscillation stop detection interrupt is generated.

Function

Oscillation stop detection

enable bit(2)

CM21

CM22

CPU clock select bit 2(3, 4)

0: Oscillation stop detect function not used

1: Oscillation stop detect function used

CM23

−

(b7-b4)

Reserved bits

Set to 0

Oscillation stop detection flag(5)

Main clock monitor flag(6)

0: Clock selected by the CM17 bit

1: On-chip oscillator clock

0: Loss of main clock not detected

1: Loss of main clock detected

0: Main clock oscillates

1: Main clock stops

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