M32CSLASH8A datasheet(102/372 Pages) RENESAS

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M32C/8A Group

9. Clock Generation Circuits

Rev.1.00

Jul 15, 2007

Page 85 of 352

REJ09B0385-0100

9.5

Power Consumption Control

The power consumption control is enabled by controlling a CPU clock frequency. The higher the CPU clock

frequency is, the more the processing power is available. The lower the CPU clock frequency is, the less power is

consumed. When unnecessary oscillation circuits are stopped, power consumption is further reduced.

CPU operating mode, wait mode, and stop mode are provided as the power consumption control. CPU operating

mode is further separated into the following modes; main clock mode, PLL mode, low-speed mode, low-power

consumption mode, on-chip oscillator mode, and on-chip oscillator low-power consumption mode.

Figure 9.13 shows a mode transition diagram.

Figure 9.13

Mode Transition

9.5.1

CPU operating mode

The CPU clock can be selected from the main clock, sub clock, on-chip oscillator clock, or PLL clock. When

switching the CPU clock source, wait until the new CPU clock source stabilizes. To change the CPU clock

source from the sub clock, on-chip oscillator clock, or PLL clock, set it to the main clock once and then switch

it to another clock.

To switch the CPU clock source from the on-chip oscillator clock to the main clock, set bits MCD4 to MCD0 in

the MCD register to 01000b (divided-by-8 mode) in on-chip oscillator mode.

Table 9.5 lists bit setting and operation mode associated with clocks.

Stop mode

Reset

Sub clock

On-chip oscillator

clock

PLL clock

CM10 = 1

Interrupt

ins

tru

ctio

Int

err

(note 1)

CM10: bit in the CM1 register

NOTE:

1. Bits MCD4 to MCD0 in the MCD register become 01000b (divide-by-8 mode) after reset.

Main clock mode

Wait mode

WAIT

instruction

Interrupt

Low-power

consumption

mode

Low-speed

mode

On-chip

oscillator mode

On-chip oscillator

low-power

consumption mode

PLL mode

WAIT instruction

Interrupt

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