H8SX1663 datasheet(439/1158 Pages) RENESAS

439 / 1158 page

Section 7 DMA Controller (DMAC)

Rev.1.00 Jun. 07, 2006 Page 387 of 1102

REJ09B0294-0100

(6) Transfer End by NMI Interrupt

When an NMI interrupt is requested, the DTE bits for all the channels are cleared to 0 and the

ERRF bit in DMDR_0 is set to 1. When an NMI interrupt is requested during a DMA transfer, the

transfer is forced to stop. To perform DMA transfer after an NMI interrupt is requested, clear the

ERRF bit to 0 and then set the DTE bits for the channels to 1.

The transfer end timings after an NMI interrupt is requested are shown below.

(a) Normal Transfer Mode and Repeat Transfer Mode

In dual address mode, a DMA transfer is completed after completion of the write cycle for one

transfer unit.

In single address mode, a DMA transfer is completed after completion of the bus cycle for one

transfer unit.

(b) Block Transfer Mode

A DMA transfer is forced to stop. Since a 1-block size of transfers is not completed, operation is

not guaranteed.

In dual address mode, the write cycle corresponding to the read cycle is performed. This is similar

to (a) in normal transfer mode.

(7) Transfer End by Address Error

When an address error occurs, the DTE bits for all the channels are cleared to 0 and the ERRF bit

in DMDR_0 is set to 1. When an address error occurs during a DMA transfer, the transfer is

forced to stop. To perform a DMA transfer after an address error occurs, clear the ERRF bit to 0

and then set the DTE bits for the channels.

The transfer end timing after an address error is the same as that after an NMI interrupt.

(8) Transfer End by Hardware Standby Mode or Reset

The DMAC is initialized by a reset and a transition to the hardware standby mode. A DMA

transfer is not guaranteed.

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