H8SX1663 datasheet(597/1158 Pages) RENESAS

Il numero della parte	H8SX1663

Spiegazioni elettronici	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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Section 10 16-Bit Timer Pulse Unit (TPU)

Rev.1.00 Jun. 07, 2006 Page 545 of 1102

REJ09B0294-0100

10.4.3

Buffer Operation

Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer

registers.

Buffer operation differs depending on whether TGR has been designated as an input capture

Table 10.29 shows the register combinations used in buffer operation.

Table 10.29 Register Combinations in Buffer Operation

Channel

Timer General Register

Buffer Register

TGRA_0

TGRC_0

TGRB_0

TGRD_0

TGRA_3

TGRC_3

TGRB_3

TGRD_3

• When TGR is an output compare register

When a compare match occurs, the value in the buffer register for the corresponding channel is

transferred to the timer general register.

This operation is illustrated in figure 10.12.

Buffer register

Timer general

TCNT

Comparator

Compare match signal

Figure 10.12 Compare Match Buffer Operation

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