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H8SX1663 Scheda tecnica(PDF) 311 Page - Renesas Technology Corp

Il numero della parte H8SX1663
Spiegazioni elettronici  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
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Produttore elettronici  RENESAS [Renesas Technology Corp]
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Section 6 Bus Controller (BSC)
Rev.1.00 Jun. 07, 2006 Page 259 of 1102
REJ09B0294-0100
6.11.6
CAS Latency Control
The CAS latency is controlled by bits W21 and W20 in WTCRB. Table 6.27 lists the setting and
CAS latency. CAS latency control cycles (Tcl) are inserted in a read cycle according to the W21
and W20 settings. WTCRB can be specified regardless of bit AST2 in ASTCR.
Figure 6.62 shows a timing example when SDRAM with a CAS latency of 3 is in use.
Bits W21 and W20 is initialized to B'11.
Table 6.27
CAS Latency Setting
W21
W20
Description
Number of CAS
Latency Cycles
0
0
Setting prohibited
1
SDRAM with CAS latency of 2 is in use
1
1
0
SDRAM with CAS latency of 3 is in use
2
1
SDRAM with CAS latency of 4 is in use
3



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