HD6432142 datasheet(133/1177 Pages) RENESAS

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Section 3 MCU Operating Modes

Rev. 4.00 Sep 27, 2006 page 89 of 1130

REJ09B0327-0400

Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash

memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2), the power-down mode control

registers (SBYCR, LPWRCR, MSTPCRH, and MSTPCRL), and the supporting module control

Bit 3

FLSHE

Description

Addresses H'(FF)FF80 to H'(FF)FF87 are used for power-down mode control register

and supporting module control register access

(Initial value)

Addresses H'(FF)FF80 to H'(FF)FF87 are used for flash memory control register

access (F-ZTAT version only)

Bit 2—Reserved: Do not write 1 to this bit.

Bits 1 and 0—Internal Clock Select 1 and 0 (ICKS1, ICKS0): These bits, together with bits

CKS2 to CKS0 in TCR, select the clock to be input to TCNT. For details, see section 12.2.4,

Timer Control Register (TCR).

3.3

Operating Mode Descriptions

3.3.1

Mode 1

The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled.

Ports 1 and 2 function as an address bus, port 3 functions as a data bus, and part of port 9 carries

bus control signals. Clearing the ABW bit to 0 in the WSCR register makes port B a data bus.

3.3.2

Mode 2

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.

After a reset, single-chip mode is set, and the EXPE bit in MDCR must be set to 1 in order to use

external addresses.

When the EXPE bit in MDCR is set to 1, ports 1, 2 and A function as input ports after a reset.

They can be set to output addresses by setting the corresponding bits in the data direction register

(DDR) to 1. Port 3 functions as a data bus, and part of port 9 carries bus control signals. Clearing

the ABW bit to 0 in the WSCR register makes port B a data bus.

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