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HD6432142 Scheda tecnica(PDF) 163 Page - Renesas Technology Corp |
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HD6432142 Scheda tecnica(HTML) 163 Page - Renesas Technology Corp |
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163 / 1177 page ![]() Section 5 Interrupt Controller Rev. 4.00 Sep 27, 2006 page 119 of 1130 REJ09B0327-0400 5.2.3 IRQ Enable Register (IER) 7 IRQ7E 0 R/W 6 IRQ6E 0 R/W 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W 3 IRQ3E 0 R/W 0 IRQ0E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W Bit Initial value Read/Write IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ7 to IRQ0. IER is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 0—IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ7 to IRQ0 are enabled or disabled. Bit n IRQnE Description 0 IRQn interrupt disabled (Initial value) 1 IRQn interrupt enabled Note: n = 7 to 0 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) • ISCRH 15 IRQ7SCB 0 R/W 14 IRQ7SCA 0 R/W 13 IRQ6SCB 0 R/W 12 IRQ6SCA 0 R/W 11 IRQ5SCB 0 R/W 8 IRQ4SCA 0 R/W 10 IRQ5SCA 0 R/W 9 IRQ4SCB 0 R/W Bit Initial value Read/Write • ISCRL 7 IRQ3SCB 0 R/W 6 IRQ3SCA 0 R/W 5 IRQ2SCB 0 R/W 4 IRQ2SCA 0 R/W 3 IRQ1SCB 0 R/W 0 IRQ0SCA 0 R/W 2 IRQ1SCA 0 R/W 1 IRQ0SCB 0 R/W Bit Initial value Read/Write |
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