HD6432142 datasheet(164/1177 Pages) RENESAS

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Section 5 Interrupt Controller

Rev. 4.00 Sep 27, 2006 page 120 of 1130

REJ09B0327-0400

ISCRH and ISCRL are 8-bit readable/writable registers that select rising edge, falling edge, or

both edge detection, or level sensing, for the input at pins

IRQ7 to IRQ0.

Each of the ISCR registers is initialized to H'00 by a reset and in hardware standby mode.

ISCRH Bits 7 to 0, ISCRL Bits 7 to 0: IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to

IRQ0 Sense Control A and B (IRQ0SCA, IRQ0SCB)

ISCRH Bits 7 to 0

ISCRL Bits 7 to 0

IRQ7SCB to

IRQ0SCB

IRQ7SCA to

IRQ0SCA

Description

Interrupt request generated at

IRQ7 to IRQ0 input low level

(Initial value)

Interrupt request generated at falling edge of

IRQ7 to IRQ0 input

Interrupt request generated at rising edge of

IRQ7 to IRQ0 input

Interrupt request generated at both falling and rising edges of

IRQ7 to IRQ0 input

5.2.5

IRQ Status Register (ISR)

IRQ7F

R/(W)*

IRQ6F

R/(W)*

IRQ5F

R/(W)*

IRQ4F

R/(W)*

IRQ3F

R/(W)*

IRQ0F

R/(W)*

IRQ2F

R/(W)*

IRQ1F

R/(W)*

Bit

Initial value

Read/Write

Note: * Only 0 can be written, to clear the flag.

ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt

requests.

ISR is initialized to H'00 by a reset and in hardware standby mode.

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