HD6432142 datasheet(177/1177 Pages) RENESAS

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Section 5 Interrupt Controller

Rev. 4.00 Sep 27, 2006 page 133 of 1130

REJ09B0327-0400

5.4.3

Operation

ABRKCR and BAR settings can be made so that an address break interrupt is generated when the

CPU prefetches the address set in BAR. This address break function issues an interrupt request to

the interrupt controller when the address is prefetched, and the interrupt controller determines the

interrupt priority. When the interrupt is accepted, interrupt exception handling is started on

completion of the currently executing instruction. With an address break interrupt, interrupt mask

control by the I and UI bits in the CPU’s CCR is ineffective.

The register settings when the address break function is used are as follows.

1. Set the break address in bits A23 to A1 in BAR.

2. Set the BIE bit in ABRKCR to 1 to enable address breaks. An address break will not be

requested if the BIE bit is cleared to 0.

When the setting condition occurs, the CMF flag in ABRKCR is set to 1 and an interrupt is

requested. If necessary, the source should be identified in the interrupt handling routine.

5.4.4

Usage Notes

• With the address break function, the address at which the first instruction byte is located

should be specified as the break address. Occurrence of the address break condition may not be

recognized for other addresses.

• In normal mode, no comparison is made with address lines A23 to A16.

• If a branch instruction (Bcc, BSR), jump instruction (JMP, JSR), RTS instruction, or RTE

instruction is located immediately before the address set in BAR, execution of this instruction

will output a prefetch signal for that address, and an address break may be requested. This can

be prevented by not making a break address setting for an address immediately following one

of these instructions, or by determining within the interrupt handling routine whether interrupt

handling was initiated by a genuine condition occurrence.

• As an address break interrupt is generated by a combination of the internal prefetch signal and

address, the timing of the start of interrupt exception handling depends on the content and

execution cycle of the instruction at the set address and the preceding instruction. Figure 5.6

shows some address timing examples.

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