HD6432142 datasheet(181/1177 Pages) RENESAS

181 / 1177 page

Section 5 Interrupt Controller

Rev. 4.00 Sep 27, 2006 page 137 of 1130

REJ09B0327-0400

Table 5.6

Interrupts Selected in Each Interrupt Control Mode

Interrupt Mask Bits

Interrupt Control Mode

Selected Interrupts

All interrupts (control level 1 has priority)

NMI and address break interrupts

All interrupts (control level 1 has priority)

NMI, address break and control level 1

interrupts

NMI, and address break interrupts

Legend:

*: Don’t care

Default Priority Determination

The priority is determined for the selected interrupt, and a vector number is generated.

If the same value is set for ICR, acceptance of multiple interrupts is enabled, and so only the

interrupt source with the highest priority according to the preset default priorities is selected and

has a vector number generated.

Interrupt sources with a lower priority than the accepted interrupt source are held pending.

Table 5.7 shows operations and control signal functions in each interrupt control mode.

Table 5.7

Operations and Control Signal Functions in Each Interrupt Control Mode

Setting

Interrupt Acceptance Control

3-Level Control

Interrupt

Control Mode

INTM1

INTM0

ICR

Default Priority

Determination

(Trace)

—

Legend:

Interrupt operation control performed

IM:

Used as interrupt mask bit

PR: Sets priority

—:

Not used

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