SH7708 datasheet(104/633 Pages) RENESAS

104 / 633 page

slot here refers to the next instruction after a delayed unconditional branch instruction, or the next

instruction when a delayed conditional branch instruction is true.

4.2.4

Exception Codes

Table 4.3 lists the exception codes written to bits 11–0 of the EXPEVT register (for reset or

general exceptions) or the INTEVT register (for general interrupt requests) to identify each

specific exception event. An additional exception register, the TRAPA (TRA) register, is used to

hold the 8-bit immediate data in an unconditional trap (TRAPA instruction).

Table 4.3

Exception Codes

Exception Type

Exception Event

Exception Code

Reset

Power-on

H'000

Manual reset

H'020

General exception events

TLB miss/invalid (load)

H'040

TLB miss/invalid (store)

H'060

Initial page write

H'080

TLB protection violation (load)

H'0A0

TLB protection violation (store)

H'0C0

Address error (load)

H'0E0

Address error (store)

H'100

Unconditional trap (TRAPA instruction)

H'160

Reserved instruction code exception

H'180

Illegal slot instruction exception

H'1A0

User break point trap

H'1E0

General interrupt requests

Nonmaskable interrupt

H'1C0

External hardware interrupts:

IRL3–IRL0 = 0000

H'200

IRL3–IRL0 = 0001

H'220

IRL3–IRL0 = 0010

H'240

IRL3–IRL0 = 0011

H'260

IRL3–IRL0 = 0100

H'280

IRL3–IRL0 = 0101

H'2A0

IRL3–IRL0 = 0110

H'2C0

IRL3–IRL0 = 0111

H'2E0

IRL3–IRL0 = 1000

H'300

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