SH7708 datasheet(108/633 Pages) RENESAS

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• The RB bit in SR is set to 1.

• An encoded value identifying the exception event is written to bits 11–0 of the EXPEVT

• Instruction execution jumps to the vector location designated by either the sum of the vector

base address and offset H'00000400 in the vector table in a TLB miss trap, or by the sum of the

vector base address and offset H'00000100 for exceptions other than TLB miss traps, to invoke

the exception handler.

4.5

Individual Exception Operations

This section describes the conditions for specific exception handling, and the processor operations.

4.5.1

Resets

• Power-On Reset

 Conditions: BREQ pin high and RESET low

 Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC = H'A0000000.

Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits are set to

1 and the IMASK field is set to B'1111. The CPU and on-chip supporting modules are

initialized. See the register descriptions in the relevant sections for details. A power-on

reset must always be performed when powering on.

• Manual Reset

 Conditions: BREQ pin low and RESET low

 Operations: EXPEVT set to H'020, VBR and SR initialized, branch to PC = H'A0000000.

Initialization sets the VBR register to H'0000000. In SR, the MD, RB, and BL bits are set

to 1 and the IMASK field is set to B'1111. The CPU and on-chip supporting modules are

initialized. See the register descriptions in the relevant sections for details.

Table 4.4

Types of Reset

Conditions for Transition

to Reset State

Internal State

Type

BREQ

RESET

CPU

On-Chip Supporting Modules

Power-on

reset

High

Low

Initialized

(See register configuration in

relevant sections)

Manual

reset

Low

Initialized

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