SH7708 datasheet(112/633 Pages) RENESAS

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4.5.3

Interrupts

• NMI

 Conditions: NMI pin edge detection

 Operations: The PC and SR after the instruction that receives the interrupt are saved to the

SPC and SSR, respectively. H'01C0 is set in INTEVT. The BL, MD, and RB bits in SR are

set to 1 and a branch occurs to PC = VBR + H'0600. This interrupt is not masked by

SR.IMASK and is accepted with top priority when the BL bit in SR is 0. When the BL bit

is 1, the interrupt is masked. See section 6, Interrupt Controller, for more information.

• IRL interrupts

 Conditions: The value of the interrupt mask bits in SR is lower than the IRL3–IRL0 level

and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary.

 Operations: The PC after the instruction that accepts the interrupt is saved to the SPC. SR at

the time the interrupt is accepted is saved to SSR. The code corresponding to the

IRL3–IRL0 level is set in INTEVT. The corresponding code is given as H'200 +

B'(IRL3–IRL0)

× H'20. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to

VBR + H'0600. The received level is not set in SR.IMASK. See section 6, Interrupt

Controller, for more information.

• On-chip module interrupts

 Conditions: The value of the interrupt mask bits in SR is lower than the on-chip module

(TMU, RTC, SCI, CPG, REF) interrupt level and the BL bit in SR is 0. The interrupt is

accepted at an instruction boundary.

 Operations: The PC after the instruction that accepts the interrupt is saved to the SPC. SR at

the time the interrupt is accepted is saved to SSR. The code corresponding to the interrupt

source is set in INTEVT. See table 6.4, Interrupt Exception Vectors and Rankings, for the

corresponding codes. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to

VBR + H'0600. B'0000 to B'1111 are set in the interrupt priority level registers (IRPA,

IRPB) within the interrupt controller. See section 6, Interrupt Controller, for more

information.

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