TDA7500 datasheet(10/14 Pages) STMICROELECTRONICS

10 / 14 page

Bit PRAM Address, PABx(15:0) is generated by

the Program Address Generator of the DSP core

for Instruction Fetching, and by the AGU in the

case of the Move Program Memory (MOVEM) In-

struction. The 24-Bit PRAM Data (Program

Code), PDBx(23:0), can only be written to using

the MOVEM instruction. During instruction fetch-

ing the PDBx Bus is routed to the Program De-

code Controller of the DSP core for instruction

decoding.

256 x 24-Bit Bootstrap ROM (PROM)

This is a 256 x 24-Bit factory programmed Boot ROM

used for storing the program sequence and for initial-

izing the DSP. Essentially this consists of reading the

data via I

2C, SPI or EMI interface and store it in

PRAM, XRAM, YRAM, and/or external DRAM.

Serial Audio Interface (SAI)

The SAI is used to deliver digital audio to the

DSPs from an external source. Once processed

by the DSPs, it can be returned through this inter-

face either sent to the DAC for D/A conversion.

The features of the SAI are listed below.

3 Synchronized Stereo Data Transmission

Lines

3 Synchronized Stereo Data Reception Lines

Master and Slave operating mode: clock lines

can be both master and slave.

Receive and Transmit Data Registers have

two locations to hold left and right data.

XCHG Interface (DSP to DSP Exchange Inter-

face)

The Exchange Interface peripheral provides bidi-

rectional communication between DSP0 and

DSP1. Both 24 bit word data and four bit Flag

data can be exchanged. A FIFO is utilized for re-

ceived data. It minimizes the number of times an

Exchange Interrupt Service Routine would have

to be called if multi-word blocks of data were to

be received. The Transmit FIFO is in effect the

Receive FIFO of the other DSP and is written di-

rectly by the transmitting DSP. The features of

the XCHG are listed below.

10 Word XCHG Receive FIFO on both DSPs

Four Flags for each XCHG for DSP to DSP

signaling

Condition flags can optionally trigger interrupts

on both DSPs

DRAM/SRAM Interface (EMI)

The External DRAM/SRAM Interface is viewed as

a memory mapped peripheral. Data transfers are

performed by moving data into/from data regis-

ters and the control is exercised by polling status

flags in the control/status register or by servicing

interrupts. An external memory write is executed

by writing data into the EMI Data Write Register.

An external memory read operation is executed

by either writing to the offset register or reading

the EMI Data Read Register, depending on the

configuration.

The features of the EMI are listed below.

Data bus width fixed at 4 bits for DRAM and 8

bits for SRAM.

Data word length 16 or 24 bits for DRAM.

Data word length 8or 16 or 24 bits for SRAM.

Thirteen DRAM address lines means 2

26 =

32MB addressable DRAM.

Refresh rate for DRAM can be chosen among

eight divider factor.

SRAM relative addressing mode; 2

22 = 4MB

addressable SRAM.

Four SRAM Timing choices.

Two Read Offset Registers.

Debug Interface

A dedicated Debug Port is available for each DSP

Cores. The debug logic is contained in the core

design of the DSP. The features of the Debug

Port are listed below:

Breakpoint Logic

Trace Logic

Single stepping

Instruction Injection

Program Disassembly

Serial Peripheral Interface

The DSP core requires a serial interface to re-

ceive commands and data over the LAN. During

an SPI transfer, data is transmitted and received

simultaneously. A serial clock line synchronizes

shifting and sampling of the information on the

two serial data lines. A slave select line allows in-

dividual selection of a slave SPI device.

When an SPI transfer occurs an 8-bit word is

shifted out one data pin while another 8-bit char-

acter is simultaneously shifted in a second data

pin.

The central element in the SPI system is the shift

single buffered in the transfer direction and dou-

ble buffered in the receive direction.

2C Interface

The inter Integrated Circuit bus is a single bidirec-

tional two-wire bus used for efficient inter IC con-

trol. All I

2C bus compatible devices incorporate

an on-chip interface which allows them communi-

cate directly with each other via the I

2C bus.

TDA7500

10/14

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