N°

NAME

TYPE

DESCRIPTION

39

SRA<2>

O

DSP SRAM Address Line<2> (Output)/DSP DRAM Address

Line<2> (Output). This pin act as the EMI address line 2 in both

SRAM Mode and DRAM Mode.

40

SRA<3>

O

DSP SRAM Address Line<3> (Output)/DSP DRAM Address

Line<3> (Output). This pin act as the EMI address line 3 in both

SRAM Mode and DRAM Mode.

41

SRA<4>

O

DSP SRAM Address Line<4> (Output)/DSP DRAM Address

Line<4> (Output). This pin act as the EMI address line 4 in both

SRAM Mode and DRAM Mode.

42

SRA<5>

O

DSP SRAM Address Line<5> (Output)/DSP DRAM Address

Line<5> (Output). This pin act as the EMI address line 5 in both

SRAM Mode and DRAM Mode.

43

SRA<6>

O

DSP SRAM Address Line<6> (Output)/DSP DRAM Address

Line<6> (Output). This pin act as the EMI address line 6 in both

SRAM Mode and DRAM Mode.

44

SRA<7>

O

DSP SRAM Address Line<7> (Output)/DSP DRAM Address

Line<7> (Output). This pin act as the EMI address line 7 in both

SRAM Mode and DRAM Mode.

45

SRA<8>

O

DSP SRAM Address Line<8> (Output)/DSP DRAM Address

Line<8> (Output). This pin act as the EMI address line 8 in both

SRAM Mode and DRAM Mode.

46

SRA<9>

O

DSP SRAM Address Line<9> (Output)/DSP DRAM Address

Line<9> (Output). This pin act as the EMI address line 9 in both

SRAM Mode and DRAM Mode.

47

SRA<10>

O

DSP SRAM Address Line<10> (Output)/DSP DRAM Address

Line<10> (Output). This pin act as the EMI address line 10 in both

SRAM Mode and DRAM Mode.

48

SRA<11>

O

DSP SRAM Address Line<11> (Output)/DSP DRAM Address

Line<11> (Output). This pin act as the EMI address line 11 in both

SRAM Mode and DRAM Mode.

49

SRA<12>

O

DSP SRAM Address Line<12> (Output)/DSP DRAM Address

Line<12> (Output). This pin act as the EMI address line 12 in both

SRAM Mode and DRAM Mode.

50

CGND2

Ground pin dedicated to the digital core part.

51

CVDD2

Supply pin dedicated to the digital core part.

52

SRA<13>

O

DSP SRAM Address Line<13> (Output)/DSP DRAM Address

Line<13> (Output). This pin act as the EMI address line 13in both

SRAM Mode and DRAM Mode.

53

SRA<14>

O

DSP SRAM Address Line<14> (Output)/DSP DRAM Address

Line<14> (Output). This pin act as the EMI address line 14 in both

SRAM Mode and DRAM Mode.

54

SRA<15>

O

DSP SRAM Address Line<15> (Output)/DSP DRAM Address

Line<15> (Output). This pin act as the EMI address line 15 in both

SRAM Mode and DRAM Mode.

55

SRA<16>/DSP0_GPIO8

O

DSP SRAM Address Line<16> (Output)/DSP DRAM Address

Line<16> (Output)/General Purpose I/O (Input/Output). This pin

acts as the EMI address line 16 in both SRAM Mode and DRAM

Mode. Optionally it can be used as general purpose I/O controlled

by DSP0.

56

DWR

O

DSP SRAM Write Enable (Output)/DRAM Write Enable (Output).

This pin serves as the write enable for the EMI in both DRAM and

SRAM Mode.

57

DRD

O

DSP SRAM Read Enable(Output)/DRAM Read Enable (Output).

This pin serves as the read enable for the EMI in both DRAM and

SRAM Mode.

PIN DESCRIPTION (continued)

TDA7500

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