N°

NAME

TYPE

DESCRIPTION

20

RDSARI_SCK/DSP1_GPIO3

O

SPI Bit Clock (Input)/ARI indicator (Output)/General Purpose I/O

(Input/Output). Schmitt trigger input. If SPI interface is enabled,

behaves as SPI bit clock. Optionally it provides the ARI indication

bit. Optionally it can be used as general purpose I/O controlled by

DSP1.

21

RDSQAL_SO/DSP1_GPIO2

O

SPI Slave Output Serial Data (Output)/RDS Bit Quality

(Output)/General Purpose I/O (Input/Output). If SPI is enabled,

behaves as Serial Data Output. Optionally it provides the RDS

serial data quality information. Optionally it can be used as general

purpose I/O controlled by DSP1.

22

RDSDAT_SI/DSP1_GPIO1

I

SPI Slave Input Serial Data (Input)/RDS Bit Data (Output)/General

Purpose I/O (Input/Output). If SPI is enabled, behaves as Serial

Data Input. Optionally it provides the RDS serial data stream.

Optionally it can be used as general purpose I/O controlled by

DSP1.

23

RDSCLK_SS/DSP1_GPIO0

I

SPI Chip Select (Input)/RDS Bit Clock (Output)/General Purpose

I/O (Input/Output). If SPI is enabled, behaves as Chip Select line

for SPI bus. Optionally it provides the 1187.5Hz RDS Bit Clock.

Optionally it can be used as general purpose I/O controlled by

DSP1.

24

INT

I

External interrupt line (Input). When this line is asserted low, the

DSP may be interrupted.

25

CGND1

Ground pin dedicated to the digital core part.

26

CVDD1

Supply pin dedicated to the digital core part.

27

SCRCCD

I

SPDIF Input 1 (Input). Stereo SPDIF input to connect a digital

audio source like a CD.

28

SCRCMD

I

SPDIF Input 2 (Input). Stereo SPDIF input to connect a digital

audio source like a MD.

29

DSRA<7>

I/O

DSP SRAM Data Lines<7> (Input/Output). When in SRAM Mode

this pin act as the EMI data line 7.

30

DSRA<6>

I/O

DSP SRAM Data Lines<6> (Input/Output). When in SRAM Mode

this pin act as the EMI data line 6.

31

DSRA<5>

I/O

DSP SRAM Data Lines<5> (Input/Output). When in SRAM Mode

this pin act as the EMI data line 5.

32

DSRA<4>

I/O

DSP SRAM Data Lines<4> (Input/Output). When in SRAM Mode

this pin act as the EMI data line 4.

33

DSRA<3>

I/O

DSP SRAM Data Line<3> (Input/Output)/DSP DRAM Data

Line<3> (Input/Output). This pin act as the EMI data line 3 in both

SRAM Mode and DRAM Mode.

34

DSRA<2>

I/O

DSP SRAM Data Line<2> (Input/Output)/DSP DRAM Data

Line<2> (Input/Output). This pin act as the EMI data line 2 in both

SRAM Mode and DRAM Mode.

35

DSRA<1>

I/O

DSP SRAM Data Line<1> (Input/Output)/DSP DRAM Data

Line<1> (Input/Output). This pin act as the EMI data line 1 in both

SRAM Mode and DRAM Mode.

36

DSRA<0>

I/O

DSP SRAM Data Line<0> (Input/Output)/DSP DRAM Data

Line<0> (Input/Output). This pin act as the EMI data line 0 in both

SRAM Mode and DRAM Mode.

37

SRA<0>

O

DSP SRAM Address Line<0> (Output)/DSP DRAM Address

Line<0> (Output). This pin act as the EMI address line 0 in both

SRAM Mode and DRAM Mode.

38

SRA<1>

O

DSP SRAM Address Line<1> (Output)/DSP DRAM Address

Line<1> (Output). This pin act as the EMI address line 1 in both

SRAM Mode and DRAM Mode.

PIN DESCRIPTION (continued)

TDA7500

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