TC7109CLW datasheet(7/21 Pages) TELCOM

7 / 21 page

3-97

TELCOM SEMICONDUCTOR, INC.

Figure 2. TC7109A Parallel Interface With 8048/8049 Microcomputer

–

GND

TEST

RUN/HOLD

STATUS

LBEN

HBEN

TC7109A

RESET

INT

PSEN

ALE

PROG

GND

P20–P27

8748/8049

CMOS

MICROCOMPUTER

+5V

OTHER I/O

+5V

GND

–5V

GND

3.58MHz

CRYSTAL

ANALOG

GND

EXTERNAL

REFERNCE

–

INPUT

0.33

µF

RINT

20k

10 k

Ω

0.2 V

1 V

XTAL2

XTALI

P14–P17

P13

P12

P11

P10

DB0–DB7

B9–B12,

POL, OR

B1–B8

CE/LOAD

21–24,

35–38

12–19

31–34

0.15

µF

INT

0.01

µF

Ω

µF

GND

+5V

GND

3–8

9–16

REF IN–

REF CAP–

REF CAP+

REF IN+

IN HI

HI LO

COM

INT

BUFF

REF OUT

OSC SEL

OSC OUT

OSC IN

SEND

BUFF OSC OUT

MODE

–

REF

Signal-Integrate Phase

The buffer and integrator inputs are removed from

common and connected to input high and input low. The

auto-zero loop is opened. The auto-zero capacitor is placed

in series in the loop to provide an equal and opposite

compensating offset voltage. The differential voltage be-

tween input high and input low is integrated for a fixed time

of 2048 clock periods. At the end of this phase, the polarity

of the integrated signal is determined. If the input signal has

no return to the converter's power supply, input low can be

tied to analog common to establish the correct common-

mode voltage.

Deintegrate Phase

Input high is connected across the previously-charged

reference capacitor and input low is internally connected to

analog common. Circuitry within the chip ensures the ca-

pacitor will be connected with the correct polarity to cause

the integrator output to return to the zero crossing (estab-

lished by auto-zero) with a fixed slope. The time, repre-

sented by the number of clock periods counted for the output

to return to zero, is proportional to the input signal.

DETAILED DESCRIPTION

(All Pin Designations Refer to 40-Pin DIP)

Analog Section

The functional diagram shows a block diagram of the

analog section of the TC7109A. The circuit will perform

conversions at a rate determined by the clock frequency

(8192 clock periods per cycle), when the RUN/HOLD input

is left open or connected to V+. Each measurement cycle is

divided into four phases, as shown in Figure 3. They are:

(1) Auto-Zero (AZ), (2) Signal Integrate (INT), (3) Reference

Deintegrate (DE), and (4) Zero Integrator (ZI).

Auto-Zero Phase

The buffer and the integrator inputs are disconnected

from input high and input low and connected to analog

common. The reference capacitor is charged to the refer-

ence voltage. A feedback loop is closed around the system

to charge the auto-zero capacitor, CAZ, to compensate for

offset voltage in the buffer amplifier, integrator, and com-

parator. Since the comparator is included in the loop, the AZ

accuracy is limited only by the noise of the system. The offset

referred to the input is less than 10

µV.

TC7109

TC7109A

12-BIT

µP-COMPATIBLE

ANALOG-TO-DIGITAL CONVERTERS

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