LTC3405 datasheet(12/16 Pages) LINER

12 / 16 page

LTC3405

3405fa

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC3405. These items are also illustrated graphically in

Figures 9 and 10. Check the following in your layout:

1. The power traces, consisting of the GND trace, the SW

trace and the VIN trace should be kept short, direct and

wide.

2. Does the VFB pin connect directly to the feedback

resistors? The resistive divider R1/R2 must be con-

nected between the (+) plate of COUT and ground.

3. Does the (+) plate of CIN connect to VIN as closely as

possible? This capacitor provides the AC current to the

internal power MOSFETs.

4. Keep the switching node, SW, away from the sensitive

VFB node.

Design Example

As a design example, assume the LTC3405 is used in a

single lithium-ion battery-powered cellular phone

application. The VIN will be operating from a maximum of

4.2V down to about 2.7V. The load current requirement

is a maximum of 0.25A but most of the time it will be in

standby mode, requiring only 2mA. Efficiency at both low

and high load currents is important. Output voltage is

2.5V. With this information we can calculate L using

equation (1),

OUT

() ∆

()

−

⎛

⎝

⎜

⎞

⎠

⎟

(3)

APPLICATIO S I FOR ATIO

Figure 9. LTC3405 Layout Diagram

RUN

LTC3405

GND

R3*

CFWD

BOLD LINES INDICATE HIGH CURRENT PATHS

*ADD R3 FOR APPLICATIONS USING A CERAMIC COUT

VIN

VOUT

3405 F09

–

MODE

VFB

VIN

CIN

–

COUT

LTC3405

GND

3405 F10

*ADD R3 WHEN USING CERAMIC COUT

PIN 1

VOUT

VIN

VFB

VIA TO VOUT

VIA TO VIN

VIA TO SW NODE

VIA TO GND

COUT

CIN

CFWD

R3*

Figure 10. LTC3405 Suggested Layout

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