TMS320VC5505 datasheet(49/141 Pages) TI

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4.4 Boot Sequence

TMS320VC5505

Fixed-Point Digital Signal Processor

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SPRS503A – JUNE 2009 – REVISED JULY 2009

The boot sequence is a process by which the device's memory is loaded with program and data sections

from external flash memory, and by which some of the device's internal registers are programmed with

predetermined values. The boot sequence is started automatically after each device reset. For more

details on device reset, see Section 6.7, Reset.

There are several methods by which the memory and register initialization can take place. Each of these

methods is referred to as a boot mode. At reset, the device cycles through different boot modes until a

valid boot signature is found (see Figure 4-1). For more information on the boot modes supported, see

Section 4.4.1, Boot Modes.

The VC5505 Bootloader follows the following steps as shown in Figure 4-1

1. Immediately after reset, the CPU fetches the reset vector from 0xFFFF00. MP/MC is 0 by default, so

0xFFFF00 is mapped to internal ROM. The PLL is in bypass mode.

2. Set CLKOUT slew rate control to slow slew rate.

3. Idle all peripherals, MPORT and HWA.

4. If CLK_SEL = 0, the Bootloader powers up the PLL and sets its output frequency to 12.288 MHz (with

a 375x multiplier using VP = 749, VS = 0, input divider disabled, output divide-by-2 enabled, and output

divider enabled with VO = 0). If CLK_SEL = 1, the Bootloader keeps the PLL bypassed.

5. Apply manufacturing trim to the bandgap references.

6. Disable CLKOUT.

7. Set Register Configuration, if present in boot image.

8. Test for NOR boot on all asynchronous CS spaces (EM_CS[2:5]) with 16-bit access:

Check the first 2 bytes read from boot signature.

If the boot signature is not valid, go to step 9.

Attempt NOR boot, go to step 17.

9. Test for NAND boot on all asynchronous CS spaces (EM_CS[2:5]) with 8-bit access:

Check the first 2 bytes read from boot table for a boot signature match.

If the boot signature is not valid, go to step 10.

Attempt NAND boot, go to step 17.

10. Test for SPI EEPROM boot on SPI_CS[0] with 500-KHz clock rate and for Parallel Port Mode on

External bus Selection Register set to 5, then set to 6:

Check the first 2 bytes read from boot table for a boot signature match.

If the boot signature is not valid, go to step 11.

Attempt SPI EEPROM boot, go to step 17.

11. Test for I2C EEPROM boot with a 7-bit slave address 0x50 and 400-kHz clock rate.

Check the first 2 bytes read from boot table for a boot signature match.

If the boot signature is not valid, go to step 12.

Attempt I2C EEPROM boot, go to step 17.

12. Test for MMC/SD boot --- MMC/SD boot is not supported.

13. Set the PLL output to approximately 36 MHz. If CLK_SEL = 1, CLKIN multiplied by 3x, ; if CLK_SEL =

0, CLKIN is multiplied by 1125x.

14. Test for UART boot --- UART boot is not supported.

15. Test for USB boot --- USB boot is not supported.

16. If the boot signature is not valid, then go back to step 14 and repeat.

17. Enable TIMER0 to start counting 200 ms.

18. Ensure a minimum of 200 ms has elapsed since step 17 before proceeding to execute the bootloaded

code.

19. Jump to the entry point specified in the boot image.

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