TMS320VC5505 datasheet(81/141 Pages) TI

81 / 141 page

6.9.1

EMIF Asynchronous Memory Support

6.9.2

EMIF Peripheral Register Description(s)

TMS320VC5505

Fixed-Point Digital Signal Processor

www.ti.com

SPRS503A – JUNE 2009 – REVISED JULY 2009

The EMIF provides an 8-bit or 16-bit data bus, an address bus width up to 21 bits, and 4 chip selects,

along with memory control signals.

The EM_A[20:15] address signals are multiplexed with the GPIO peripheral and controlled by the External

Bus Selection Register (EBSR). For more detail on the pin muxing, see the Section 4.6.1, External Bus

Selection Register (EBSR). For more information on the VC5505 EMIF, see the TMS320VC5505 DSP

External Memory Interface (EMIF) User's Guide (literature number SPRUFO8).

The EMIF supports asynchronous:

• SRAM memories

• NAND Flash memories

• NOR Flash memories

The EMIF data bus can be configured for both 8- or 16-bit width. The device supports up to 21 address

lines and four external wait/interrupt inputs. Up to four asynchronous chip selects are supported by EMIF

(EM_CS[5:2]).

Each chip select has the following individually programmable attributes:

• Data bus width

• Read cycle timings: setup, hold, strobe

• Write cycle timings: setup, hold, strobe

• Bus turn around time

• Extended Wait Option With Programmable Timeout

• Select Strobe Option

• NAND flash controller supports 1-bit and 4-bit ECC calculation on blocks of 512 bytes

Table 6-11 shows the EMIF registers.

For more detailed information on the EMIF and its registers, see the TMS320VC5505 External Memory

Interface (EMIF) User's Guide (literature number SPRUFO8).

Table 6-11. External Memory Interface (EMIF) Peripheral Registers(1)

HEX ADDRESS

ACRONYM

RANGE

1000h

REV

Revision Register

1001h

STATUS

Status Register

1004h

AWCCR1

Asynchronous Wait Cycle Configuration Register 1

1005h

AWCCR2

Asynchronous Wait Cycle Configuration Register 2

1010h

ACS2CR1

Asynchronous CS2 Configuration Register 1

1011h

ACS2CR2

Asynchronous CS2 Configuration Register 2

1014h

ACS3CR1

Asynchronous CS3 Configuration Register 1

1015h

ACS3CR2

Asynchronous CS3 Configuration Register 2

1018h

ACS4CR1

Asynchronous CS4 Configuration Register 1

1019h

ACS4CR2

Asynchronous CS4 Configuration Register 2

101Ch

ACS5CR1

Asynchronous CS5 Configuration Register 1

101Dh

ACS5CR2

Asynchronous CS5 Configuration Register 2

1040h

EIRR

EMIF Interrupt Raw Register

1044h

EIMR

EMIF Interrupt Mask Register

(1)

Before reading or writing to the EMIF registers, be sure to set the BYTEMODE bits to 00b in the EMIF system control register to enable

word accesses to the EMIF registers.

Submit Documentation Feedback

Peripheral Information and Electrical Specifications

TMS320VC5505 Scheda tecnica(PDF) 81 Page - Texas Instruments

TMS320VC5505 Scheda tecnica(HTML) 81 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL