TVP6000CPFP datasheet(32/57 Pages) TI

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2–20

2.11.9

BLANK_LEVEL

Subaddress: 5E Default: 0xB8

GV8

BLANK[6:0]

Where:

GV8

The most significant bit of the GAIN_V register. See the GAIN_V register for more

information.

BLANK[6:0]Blank level setting for NTSC = 0x38 and for PAL = 0x3C.

2.11.10 GAIN_Y

Subaddress: 5F Default: 0x2E

GY(7–0)

Where:

GY[7:0]

Gain control of Y signal. The MSB, bit 8, is located at subaddress 60, bit 5.

In the case of NTSC with a 7.5 IRE pedestal, WHITE – BLACK = 92.5 IRE.

Gain_Y = 0x12E

In the case of no pedestal (PAL/SECAM), WHITE – BLACK = 100 IRE.

Gain_Y = 0x145

2.11.11 X_COLOR

Subaddress: 60 Default: 0x20

GY8

LCD(2–0)

Cross color and chroma delay compensation register

Where:

Cross color reduction enable for composite video output. Cross color does not affect

S-video output

Cross color reduction is disabled (default)

Cross color reduction is enabled

GY8

MSB of Gain_Y register.

LCD[2:0]

These three bits can be used for chroma channel delay compensation during S-video

mode. Table 2–10 shows the delay corresponding to the LCD[2:0] settings.

Table 2–10. Chroma Channel Delays

LCD[2:0]

DELAY ON CHROMA

CHANNEL

0.5 pixel clock period

1 pixel clock period

1.5 pixel clock period

2 pixel clock period

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