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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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STM32W108CB Scheda tecnica(PDF) 125 Page - STMicroelectronics |
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STM32W108CB Scheda tecnica(HTML) 125 Page - STMicroelectronics |
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125 / 179 page  STM32W108CB, STM32W108HB General-purpose timers Doc ID 16252 Rev 2 125/179 8.3.10 Timer x auto-reload register (TIMx_ARR) Address offset: 0xE02C (TIM1) and 0xF02C (TIM2) Reset value: 0x0000 0000 8.3.11 Timer x capture/compare 1 register (TIMx_CCR1) Address offset: 0xE034 (TIM1) and 0xF034 (TIM2) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIM_ARR rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw [15:0] TIM_ARR: Auto-reload value TIM_ARR is the value to be loaded in the shadow auto-reload register. The auto-reload register is buffered. Writing or reading the auto-reload register accesses the buffer register. The content of the buffer register is transfered in the shadow register permanently or at each update event UEV, depending on the auto-reload buffer enable bit (TIM_ARBE) in TMRx_CR1 register. The update event is sent when the counter reaches the overflow point (or underflow point when down-counting) and if the TIM_UDIS bit equals 0 in the TMRx_CR1 register. It can also be generated by software. The counter is blocked while the auto-reload value is 0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIM_CCR rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw [15:0] TIM_CCR: Capture/compare value If the CC1 channel is configured as an output (TIM_CC1S = 0): TIM_CCR1 is the buffer value to be loaded in the actual capture/compare 1 register. It is loaded permanently if the preload feature is not selected in the TMR1_CCMR1 register (bit OC1PE). Otherwise the buffer value is copied to the shadow capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TMR1_CNT and signaled on the OC1 output. If the CC1 channel is configured as an input (TIM_CC1S is not 0): CCR1 is the counter value transferred by the last input capture 1 event (IC1). |
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