STM32W108CB datasheet(5/179 Pages) STMICROELECTRONICS

5 / 179 page

STM32W108CB, STM32W108HB

Contents

Doc ID 16252 Rev 2

5/179

7.3.3

SPI status register (SCx_SPISTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

7.3.4

Serial clock linear prescaler register (SCx_RATELIN) . . . . . . . . . . . . . . 68

7.3.5

Serial clock exponential prescaler register (SCx_RATEEXP) . . . . . . . . 68

7.4

SPI slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

7.5

Two wire (TWI) serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

7.5.1

TWI status register (SCx_TWISTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

7.5.2

TWI control 1 register (SCx_TWICTRL1) . . . . . . . . . . . . . . . . . . . . . . . 69

7.5.3

TWI control 2 register (SCx_TWICTRL2) . . . . . . . . . . . . . . . . . . . . . . . 70

7.6

Universal asynchronous receiver / transmitter (UART) registers . . . . . . . 70

7.6.1

UART status register (SC1_UARTSTAT) . . . . . . . . . . . . . . . . . . . . . . . . 70

7.6.2

UART configuration register (SC1_UARTCFG) . . . . . . . . . . . . . . . . . . . 71

7.6.3

UART baud rate period register (SC1_UARTPER) . . . . . . . . . . . . . . . . 72

7.6.4

UART baud rate fractional period register (SC1_UARTFRAC) . . . . . . . 72

7.7

DMA channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

7.7.1

Serial DMA control register (SCx_DMACTRL) . . . . . . . . . . . . . . . . . . . 72

7.7.2

Serial DMA status register (SCx_DMASTAT) . . . . . . . . . . . . . . . . . . . . 73

7.7.3

Transmit DMA begin address register A (SCx_TXBEGA) . . . . . . . . . . . 75

7.7.4

Transmit DMA begin address register B (SCx_TXBEGB) . . . . . . . . . . . 75

7.7.5

Transmit DMA end address register A (SCx_TXENDA) . . . . . . . . . . . . 75

7.7.6

Transmit DMA end address register B (SCx_TXENDB) . . . . . . . . . . . . 76

7.7.7

Transmit DMA count register (SCx_TXCNT) . . . . . . . . . . . . . . . . . . . . . 76

7.7.8

Receive DMA begin address register A (SCx_RXBEGA) . . . . . . . . . . . 76

7.7.9

Receive DMA begin address register B (SCx_RXBEGB) . . . . . . . . . . . 77

7.7.10

Receive DMA end address register A (SCx_RXENDA) . . . . . . . . . . . . . 77

7.7.11

Receive DMA end address register B (SCx_RXENDB) . . . . . . . . . . . . . 77

7.7.12

Receive DMA count register A (SCx_RXCNTA) . . . . . . . . . . . . . . . . . . 78

7.7.13

Receive DMA count register B (SCx_RXCNTB) . . . . . . . . . . . . . . . . . . 78

7.7.14

Saved receive DMA count register (SCx_RXCNTSAVED) . . . . . . . . . . 78

7.7.15

DMA first receive error register A (SCx_RXERRA) . . . . . . . . . . . . . . . . 79

7.7.16

DMA first receive error register B (SCx_RXERRB) . . . . . . . . . . . . . . . . 79

General-purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

8.1

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

8.1.1

Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

8.1.2

Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

8.1.3

Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

8.1.4

Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

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