STM32W108CB datasheet(143/179 Pages) STMICROELECTRONICS

143 / 179 page

STM32W108CB, STM32W108HB

Interrupts

Doc ID 16252 Rev 2

143/179

Interrupts

The STM32W108's interrupt system is composed of two parts: a standard ARM® Cortex-

M3 Nested Vectored Interrupt Controller (NVIC) that provides top level interrupts, and an

Event Manager (EM) that provides second level interrupts. The NVIC and EM provide a

simple hierarchy. All second level interrupts from the EM feed into top level interrupts in the

NVIC. This two-level hierarchy allows for both fine granular control of interrupt sources and

coarse granular control over entire peripherals, while allowing peripherals to have their own

interrupt vector.

The Section 10.3: Nested vectored interrupt controller (NVIC) interrupts provides a

description of the NVIC and an overview of the exception table (ARM nomenclature refers to

interrupts as exceptions) and Section 10.2: Event manager provides a more detailed

description of the Event Manager including a table of all top-level peripheral interrupts and

their second-level interrupt sources.

In practice, top-level peripheral interrupts are only used to enable or disable interrupts for an

entire peripheral. Second-level interrupts originate from hardware sources, and therefore

are the main focus of applications using interrupts.

10.1

Nested vectored interrupt controller (NVIC)

The ARM® Cortex-M3 Nested Vectored Interrupt Controller (NVIC) facilitates low-latency

exception and interrupt handling. The NVIC and the processor core interface are closely

coupled, which enables low-latency interrupt processing and efficient processing of late

arriving interrupts. The NVIC also maintains knowledge of the stacked (nested) interrupts to

enable tail-chaining of interrupts.

The ARM® Cortex-M3 NVIC contains 10 standard interrupts that are related to chip and

CPU operation and management. In addition to the 10 standard interrupts, it contains 17

individually vectored peripheral interrupts specific to the STM32W108.

The NVIC defines a list of exceptions. These exceptions include not only traditional

peripheral interrupts, but also more specialized events such as faults and CPU reset. In the

ARM® Cortex-M3 NVIC, a CPU reset event is considered an exception of the highest

priority, and the stack pointer is loaded from the first position in the NVIC exception table.

The NVIC exception table defines all exceptions and their position, including peripheral

interrupts. The position of each exception is important since it directly translates to the

location of a 32-bit interrupt vector for each interrupt, and defines the hardware priority of

exceptions. Each exception in the table is a 32-bit address that is loaded into the program

counter when that exception occurs. Table 21 lists the entire exception table. Exceptions 0

(stack pointer) through 15 (SysTick) are part of the standard ARM® Cortex-M3 NVIC, while

exceptions 16 (Timer 1) through 32 (Debug) are the peripheral interrupts specific to the

STM32W108 peripherals. The peripheral interrupts are listed in greater detail in Table 22.

Table 21.

NVIC exception table

Exception

Position

Description

Stack top is loaded from first entry of vector table on reset.

Reset

Invoked on power up and warm reset. On first instruction, drops to

lowest priority (Thread mode). Asynchronous.

STM32W108CB Scheda tecnica(PDF) 143 Page - STMicroelectronics

STM32W108CB Scheda tecnica(HTML) 143 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL