MPC8377E datasheet(28/124 Pages) FREESCALE

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MPC8377E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC)

8.2.3

RMII AC Timing Specifications

This section describes the RMII transmit and receive AC timing specifications.

8.2.3.1

RMII Transmit AC Timing Specifications

The RMII transmit AC timing specifications are in Table 28.

Figure 12 shows the RMII transmit AC timing diagram.

Figure 12. RMII Transmit AC Timing Diagram

Table 28. RMII Transmit AC Timing Specifications

At recommended operating conditions with LVDD of 3.3 V ± 5%.

Parameter

Symbol1

Min

Typical

Max

Unit

REF_CLK clock period

tRMT

15.020.025.0

REF_CLK duty cycle

tRMTH

REF_CLK peak-to-peak jitter

tRMTJ

—

250

Rise time REF_CLK (20%–80%)

tRMTR

1.0

—

2.0

Fall time REF_CLK (80%–20%)

tRMTF

1.0

—

2.0

REF_CLK to RMII data TXD[1:0], TX_EN delay

tRMTDX

2.0

—

10.0

Note:

1 The symbols used for timing specifications herein follow the pattern of t

(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII

transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in

general, the clock reference symbol representation is based on two to three letters representing the clock of a particular

functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

REF_CLK

TXD[1:0]

tRMTDX

tRMT

tRMTH

tRMTR

tRMTF

TX_EN

TX_ER

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