MPC8377E datasheet(84/124 Pages) FREESCALE

84 / 124 page

MPC8377E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular

clock driver chip.

Figure 58. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)

Figure 59 shows the SerDes reference clock connection reference circuits for a single-ended clock driver.

It assumes the DC levels of the clock driver are compatible with device SerDes reference clock input’s DC

requirement.

Figure 59. Single-Ended Connection (Reference Only)

21.2.4

AC Requirements for SerDes Reference Clocks

The clock driver selected should provide a high quality reference clock with low phase noise and

cycle-to-cycle jitter. Phase noise less than 100 KHz can be tracked by the PLL and data recovery loops and

is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise

n_REF_CLK

Clock Driver

100

Ω differential PWB trace

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

LVPECL CLK Driver Chip

10 nF

MPC8377E

n_REF_CLK

100

Ω differential PWB trace

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

Single-Ended CLK

Driver Chip

Total 50

Ω. Assume clock driver’s

output impedance is about 16

Ω.

MPC8377E

MPC8377E Scheda tecnica(PDF) 84 Page - Freescale Semiconductor, Inc