MPC8378E datasheet(63/126 Pages) FREESCALE

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MPC8378E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

PCI

Table 54 shows the PCI AC timing specifications at 33 MHz.

Input hold from Clock

tPCIXKH

0.25

—

2, 4, 6

Output Clock Skew

tPCKOSK

—0.5

Notes:

1 Note that the symbols used for timing specifications herein follow the pattern of t

(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH

symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN

clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to

the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.

2 See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.

3 For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

4 Input timings are measured at the pin.

5 PCI specifications allows 1 ns skew for 66 MHz but includes the total allowed skew, board, connectors, etc.

6 Value does not comply with the PCI 2.3 Local Bus Specifications.

Table 54. PCI AC Timing Specifications at 33 MHz

PCI_SYNC_IN clock input levels are with next levels: VIL = 0.1

× OVDD, VIH = 0.7 × OVDD.

Parameter

Symbol1

Min

Max

Unit

Notes

Clock to output valid

tPCKHOV

—11

Output hold from Clock

tPCKHOX

2—

Clock to output high impedance

tPCKHOZ

—14

2, 3

Input setup to Clock

tPCIVKH

3.0

—

2, 4

Input hold from Clock

tPCIXKH

0.25

—

2, 4, 6

Output Clock skew

tPCKOSK

—0.5

Note:

1 Note that the symbols used for timing specifications herein follow the pattern of t

(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH

symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN

clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to

the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.

2 See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.

3 For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

4 Input timings are measured at the pin.

5 PCI specifications allows 2 ns skew for 33 MHz but includes the total allowed skew, board, connectors, etc.

6 Value does not comply with the PCI 2.3 Local Bus Specifications.

Table 53. PCI AC Timing Specifications at 66 MHz (continued)

PCI_SYNC_IN clock input levels are with next levels: VIL = 0.1

× OVDD, VIH = 0.7 × OVDD.

Parameter

Symbol1

Min

Max

Unit

Notes

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