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LAN9311 Scheda tecnica(PDF) 7 Page - SMSC Corporation |
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LAN9311 Scheda tecnica(HTML) 7 Page - SMSC Corporation |
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7 / 459 page  Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN9311/LAN9311i 7 Revision 1.6 (08-18-09) DATASHEET 10.2.3.7 WRITE (Write Location) ................................................................................................................................................................................ 149 10.2.3.8 WRAL (Write All)........................................................................................................................................................................................... 149 10.2.4 EEPROM Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.2.4.1 EEPROM Loader Operation ......................................................................................................................................................................... 150 10.2.4.2 EEPROM Valid Flag ..................................................................................................................................................................................... 152 10.2.4.3 MAC Address................................................................................................................................................................................................ 152 10.2.4.3.1Host MAC Address Reload ......................................................................................................152 10.2.4.4 Soft-Straps .................................................................................................................................................................................................... 152 10.2.4.4.1PHY Registers Synchronization ...............................................................................................152 10.2.4.4.2Virtual PHY Registers Synchronization....................................................................................153 10.2.4.4.3LED and Manual Flow Control Register Synchronization ........................................................153 10.2.4.5 Register Data ................................................................................................................................................................................................ 153 10.2.4.6 EEPROM Loader Finished Wait-State.......................................................................................................................................................... 154 10.2.4.7 Reset Sequence and EEPROM Loader........................................................................................................................................................ 154 Chapter 11 IEEE 1588 Hardware Time Stamp Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 11.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 11.1.1 IEEE 1588 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 11.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 11.2 IEEE 1588 Time Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 11.2.1 Capture Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 11.2.2 PTP Message Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 11.3 IEEE 1588 Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 11.4 IEEE 1588 Clock/Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 11.5 IEEE 1588 GPIOs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 11.6 IEEE 1588 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Chapter 12 General Purpose Timer & Free-Running Clock. . . . . . . . . . . . . . . . . . . . . . . . 162 12.1 General Purpose Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 12.2 Free-Running Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Chapter 13 GPIO/LED Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 13.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 13.2 GPIO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 13.2.1 GPIO IEEE 1588 Timestamping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 13.2.1.1 IEEE 1588 GPIO Inputs ................................................................................................................................................................................ 164 13.2.1.2 IEEE 1588 GPIO Outputs ............................................................................................................................................................................. 164 13.2.2 GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 13.2.2.1 GPIO Interrupt Polarity.................................................................................................................................................................................. 164 13.2.2.2 IEEE 1588 GPIO Interrupts........................................................................................................................................................................... 165 13.3 LED Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Chapter 14 Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 14.1 TX/RX FIFO Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 14.1.1 TX/RX Data FIFO’s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 14.1.2 TX/RX Status FIFO’s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 14.1.3 Direct FIFO Access Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 14.2 System Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 14.2.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 14.2.1.1 Interrupt Configuration Register (IRQ_CFG) ................................................................................................................................................ 173 14.2.1.2 Interrupt Status Register (INT_STS)............................................................................................................................................................. 175 14.2.1.3 Interrupt Enable Register (INT_EN).............................................................................................................................................................. 178 14.2.1.4 FIFO Level Interrupt Register (FIFO_INT) .................................................................................................................................................... 180 14.2.2 Host MAC & FIFO’s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 14.2.2.1 Receive Configuration Register (RX_CFG) .................................................................................................................................................. 181 14.2.2.2 Transmit Configuration Register (TX_CFG).................................................................................................................................................. 183 14.2.2.3 Receive Datapath Control Register (RX_DP_CTRL).................................................................................................................................... 184 14.2.2.4 RX FIFO Information Register (RX_FIFO_INF) ............................................................................................................................................ 185 14.2.2.5 TX FIFO Information Register (TX_FIFO_INF)............................................................................................................................................. 186 14.2.2.6 Host MAC RX Dropped Frames Counter Register (RX_DROP)................................................................................................................... 187 14.2.2.7 Host MAC CSR Interface Command Register (MAC_CSR_CMD)............................................................................................................... 188 14.2.2.8 Host MAC CSR Interface Data Register (MAC_CSR_DATA) ...................................................................................................................... 189 14.2.2.9 Host MAC Automatic Flow Control Configuration Register (AFC_CFG) ...................................................................................................... 190 |
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